[VHDL2019 Feature Request] Allow Partially Connected Vectors in portmaps

[richardhead]

Previously, output ports in port maps needed to be wholly connected or left open. In VHDL 2019, this is no longer a requirement. Please implement this feature.

greatness : entity some_lib.some_ent
port map (
  some_output(7 downto 4) => some_4bit_signal,
  some_output(3 downto 0) => open
);

[bitjockey]

Until then....

some_output(3 downto 0) => dummy_signal_that_goes_nowhere_because_vivado_is_stupid

[Avtx]

+1

[maps-mpls]

> Previously, output ports in port maps needed to be wholly connected or left open.  In VHDL 2019, this is no longer a requirement. 

Wow, I did not know they added that. 

greatness : entity some_lib.some_ent
port map (
  some_output(7 downto 4) => some_4bit_signal,
  some_output(3 downto 0) => open
);

And are you implying they are left justifying for port maps of different widths, or was that a misunderstanding on my part.  Do you mean they allowed this:

greatness : entity some_lib.some_ent
port map (
  some_output=> some_4bit_signal, -- this would be a terrible idea if some_output were more than 4 bits
  --some_output(3 downto 0) => open
);

Or this:

greatness : entity some_lib.some_ent
port map (
  some_output(7 downto 4) => some_4bit_signal,
--  some_output(3 downto 0) => open
);

This last one would be okay.  The previous would be terrible. 

Anyway, if they allow port mapping of ports to signals or ports of different sizes, and zeropadd, sign extend, or left justify, VHDL 2019 would became my least favorite language. 

Sorry for the rant, but we have been living in clown world lately and I hope it is the later and not the former.

[richardhead]

@maps-mpls 

Its partial port mapping. Sizes must still match. VHDL 2008 and previous require a signal to be wholly mapped, even if you only want part of it.

VHDL 2008:

signal a,b,c,d : std_logic;
signal whole_port_signal : std_logic_vector;

port map (
  some_8_bit_op_port => whole_port_signal,
.. 
);

a <= whole_port_signal(0);
b <= whole_port_signal(2);
c <= whole_port_signal(4);
d <= whole_port_signal(6);

VHDL 2019:

signal a,b,c,d : std_logic;

port map (
  some_8_bit_op_port(0) => a,
  some_8_bit_op_port(2) => b,
  some_8_bit_op_port(4) => c,
  some_8_bit_op_port(6) => d
);

It might make more sense with record type ports:

signal axis_tdata  : std_logic_vector(64 downto 0);
signal axis_tvalid : std_logic;

port map (
  some_axis_record.tkeep => open,
  some_axis_record.tdata => axis_tdata,
  some_axis_record.tvalid => axis_tvalid
);