[VHDL2019 Feature Request] Allow Partially Connected Vectors in portmaps

[richardhead]

Previously, output ports in port maps needed to be wholly connected or left open. In VHDL 2019, this is no longer a requirement. Please implement this feature.

greatness : entity some_lib.some_ent
port map (
  some_output(7 downto 4) => some_4bit_signal,
  some_output(3 downto 0) => open
);

[bitjockey]

Until then....

some_output(3 downto 0) => dummy_signal_that_goes_nowhere_because_vivado_is_stupid