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Scholar
Scholar
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Registered: ‎08-01-2012

[VHDL2019 Feature Request] Expanded Conditional Expression - signal initialsation, function returns and unaffected keyword.

I was previously instructed to request VHDL features one per post, so here we go. Im looking for the initial quality of life features of VHDL 2019 and I only care about support in synthesis.

Please add support for conditional expressions during initialisation and function returns.

eg.

signal s : std_logic_vector := x"00" when G_INIT_ALL_ZERO else x"11";

function return:

function get_s(all_zero : boolean) return std_logic_vector is
begin
  return x"00" when all_zero else x"FF";
end function;

and unaffected keyword:

s <= '1' when something else '0' when something_else else unaffected;
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