I was previously instructed to request VHDL features one per post, so here we go. Im looking for the initial quality of life features of VHDL 2019 and I only care about support in synthesis.
Please add support for conditional expressions during initialisation and function returns.
signal s : std_logic_vector := x"00" when G_INIT_ALL_ZERO else x"11";
function get_s(all_zero : boolean) return std_logic_vector is
return x"00" when all_zero else x"FF";
and unaffected keyword:
s <= '1' when something else '0' when something_else else unaffected;