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Scholar
Scholar
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Registered: ‎08-01-2012

[VHDL2019 Feature Request] Infer Subtype from initial Value

I was previously instructed to request VHDL features one per post, so here we go. Im looking for the initial quality of life features of VHDL 2019 and I only care about support in synthesis.

Please can I request that signal/variable subtypes can be infered from the initial value:

example:

 

signal s : std_logic_vector := x"00"; -- infers range (0 to 7)

 

 

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