I was previously instructed to request VHDL features one per post, so here we go. Im looking for the initial quality of life features of VHDL 2019 and I only care about support in synthesis.
Please implement the ability for ports to read other ports in a port declaration.
entity my_awesome_VHDL2019_entity is
s1 : in std_logic_vector(9000 downto 0);
s2 : s1'subtype