UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
4,373 Views
Registered: ‎11-27-2016

VIO IP Addition

Hello,

            I am using Aurora Example design for SFP. In this I need VIO for debugging the signal. I have added the VIO IP in Example design. I don't know how to instantiate this VIO into aurora IP? I have pasted the "vio_0.veo" into main verilog hierarchy module(Aurora). can anyone tell me the steps?

 

Thanks,

Abinaya

0 Kudos
4 Replies
Moderator
Moderator
4,351 Views
Registered: ‎07-01-2015

Re: VIO IP Addition

Hi abinaya1991@,

 

You can use the instantiation template of the VIO and port map the signal you want to debug to i/p of VIO 

Please go through lab-3 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug936-vivado-tutorial-programming-debugging.pdf

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
4,302 Views
Registered: ‎08-01-2012

Re: VIO IP Addition

What is FPGA device part are you using? Also let us know which version Xilinx tools are you using? Based on that we can give more focused guidelines? 

 

Also refer the below link documents and check whether they are useful for you

https://www.xilinx.com/support/answers/58605.html

https://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf

https://www.xilinx.com/support/answers/54367.html  

 

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Explorer
Explorer
4,293 Views
Registered: ‎11-27-2016

Re: VIO IP Addition

Hi,

       I am using  KINTEX 7(xc7k160tffg676)  and KC705 (xc7k325tffg900) FPGA for SFP. I need to monitor the hard error status through VIO IP. I have to map these signals to VIO inputs. After instantiating the vio in aurora main module its showing

 "[Synth 8-4442] BlackBox module vio_0 has unconnected pin clk". 

 

I am using vivado 2015.4

 

 

Thanks,

Abinaya

0 Kudos
Moderator
Moderator
4,263 Views
Registered: ‎07-01-2015

Re: VIO IP Addition

Hi abinaya1991@,

 

Can you please check the connection of clock pin of VIO?

Connect it to a free running clock source.

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos