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Observer
Observer
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Registered: ‎12-21-2015

VIVADO 2018.3 synthesis optimises too much logic away

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hello,

I am trying to synthesize and implement my design to Genesys 2 board ( kintex fpga) using Vivado 2018.3.

My whole design is written in System verilog and it has been implemented to IC but not to FPGA.

In Vivado the elaborated design is quite right, but the synhesized design is not.  A lot of logic is removed. I suspect that it is because there is something wrong with the padlevel i.e the inputs and outputs are not connected and therefore the synthesis optimises away a lot of logic.

 

How should I handle the padlevel?  The design has a pad_frame module, which contains pads :

    pad_functional_pd padinst_sdio_data0 (.OEN(~oe_sdio_data0_i ), .I(out_sdio_data0_i ), .O(in_sdio_data0_o ), .PAD(pad_sdio_data0 ), .PEN(~pad_cfg_i[22][0]) );

 

pad_functional_pd is in separate .sv file and looks like this::

module pad_functional_pd
(
   input  logic             OEN,
   input  logic             I,
   output logic             O,
   input  logic             PEN,
   inout  logic             PAD
);

/*
    X Unknown
    Z Hi-Z
    H Pull High
    L Pull Low
*/

/*
    OEN I   PAD PEN | PAD O
                    |
    0   0   -   0/1 | 0   0
    0   1   -   0/1 | 1   1
    1   0/1 0   0/1 | -   0
    1   0/1 1   0/1 | -   1
    1   0/1 Z   0   | L   L
    1   0/1 Z   1   | -   X

*/

  wire   PAD_wi;

  bufif0 (PAD, I, OEN);
  buf    (O, PAD);
  bufif0 (PAD_wi, 1'b0, PEN);
//  rpmos  (PAD, PAD_wi, 1'b0); ( this i had to comment because it was not synthesisable

 

regards, skor

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Observer
Observer
428 Views
Registered: ‎12-21-2015
problem solved . cancellin questin
Regards , skor

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Highlighted
Observer
Observer
429 Views
Registered: ‎12-21-2015
problem solved . cancellin questin
Regards , skor

View solution in original post

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