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Newbie
Newbie
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Registered: ‎07-09-2020

VIVADO 2020.1: Attribute ASYNC_REG set to "FALSE" prevents insertion of SRL16

The following code highlights the problem. Although the ASYNC_REG feature is set to "FALSE", no shift register is used and the code becomes huge.

library ieee;
use ieee.std_logic_1164.all;

entity test_ff is
generic (
   delay : positive := 512 );
port (
   clk : in std_logic;
   reset : in std_logic;
   x : in std_logic;
   y : out std_logic );
end test_ff;

architecture rtl of test_ff is

signal x_sr : std_logic_vector(delay-1 downto 0) := (others => '0');

attribute ASYNC_REG : string;
attribute ASYNC_REG of x_sr : signal is "FALSE";

begin

y <= x_sr(0);

process(clk)
begin
   if rising_edge(clk) then
      x_sr <= x & x_sr(delay-1 downto 1);
   end if;
end process;

end rtl;

If the attribute is left out completely, the synthesized code is only 5 slices versus over 100 slices. I wanted to use code like this to be able to infer a variable-length-flipflop with async set or unset. But because the attribute, by just be being there, prevents the insertion, I cannot use such code as shown below (using a generic to set async_reg). Looks like a bug in Vivado.

library ieee;
use ieee.std_logic_1164.all;

entity test_ff is
generic (
   delay : positive := 512;
   async_opt : string := "FALSE" );
port (
   clk : in std_logic;
   reset : in std_logic;
   x : in std_logic;
   y : out std_logic );
end test_ff;

architecture rtl of test_ff is

signal x_sr : std_logic_vector(delay-1 downto 0) := (others => '0');

attribute ASYNC_REG : string;
attribute ASYNC_REG of x_sr : signal is async_opt;

begin

y <= x_sr(0);

process(clk)
begin
   if rising_edge(clk) then
      x_sr <= x & x_sr(delay-1 downto 1);
   end if;
end process;

end rtl;

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2 Replies
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Moderator
Moderator
167 Views
Registered: ‎11-09-2015

HI @MaximPiz 

I have checked internally and indeed this seems to be an issue in vivado. It seems that was found internally so it was already reported.

However, it seems that it was too late to make it for 2020.2 and the fix will only make it for 2021.1.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Newbie
Newbie
162 Views
Registered: ‎07-09-2020

Hi @florentw 

thanks for your message and how it will be resolved.

Best regards.

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