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Visitor
Visitor
4,909 Views
Registered: ‎06-28-2016

VIvado 2016.2: BRAM connection and instantiation problems ([BD 41-237], [Memdata 28-122] and [Memdata 28-96])

So before explaining my problem let my say, that I am aware that parts of this issue have been posted multiple times, but there was either no solution found or the solution doesn't work on my case.
My design is this:
I have a BRAM that will be used as a look-up so what I want is to initialize it once, and then just read from different addresses.

I am using a Block Memory Generator which then I configure it as a Simple Dual Port RAM (in Stand Alone mode).

On PORT A i have connected an AXI Bram Controller (on AXI4Lite protocol connection with AXI Interconnect) and on PORT B my custom (HLS generated) IP.

 

Since the first bitstream generation attempt I got this critical warning from validation:

[BD 41-237]: Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_0/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL)

 

and this error during bitstream gen:

[Memdata 28-96] Could not find a BMM_INFO_DESIGN property in the design. Could not generate the merged BMM file.

 

I then tried the write_mmi.tcl solution suggested here (for the same Memdata error but for a Microblaze design, mine uses a Zynq) and although the script runs (i kinda randomly changed the processor name to "processing_system7_0" wasn't sure with what to replace "microblaze") the problems still remain along with a new one which reads:

[Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.

 

Anyone got any clues regarding what might be the problem (or even where to start looking for it)?

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Xilinx Employee
Xilinx Employee
4,868 Views
Registered: ‎08-01-2008

check this ARs
https://www.xilinx.com/support/answers/59442.html
Thanks and Regards
Balkrishan
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Visitor
Visitor
4,849 Views
Registered: ‎06-28-2016

@balkris thanks for replying.
However, this suggestion is for a BRAM embedded to the custom IP where ports and interfaces can be customized from the "IP Packager". My BRAM is outside of my HLS IP (and my IP just has a port with a BRAM interface). So the "Edit IP Packager" isn't an option neither for the BRAM IP nor for the AXI_BRAM_CONTROLLER IP.

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Visitor
Visitor
2,946 Views
Registered: ‎10-03-2017

I am facing a similar issue. Was this resolved?

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