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Newbie sage12
Newbie
104 Views
Registered: ‎09-20-2018

Variable assignment inside a VHDL process in Synthesis

Hi all,

 

I'm a newbie in VHDL design. I have a doubt regarding different assignations to the same variable inside a process in a post-synthesized design.

 

For example the next code snippet:

 

--previous code

p1 : process (clk,reset)

  variable a : std_logic;
  variable b : std_logic;

begin
  a := '1'
  
 --some code here that modifies b variable

  if ( b = '1') then
    a := '0';
  end if;

end process;

--the code goes on

Can it be assured that during execution in FPGA, if b is '1', a always will be '0'. In other words, I know that during simulation all statements inside a process are executed sequentially, but can we say the same in relation to a synthesized design? Is the execution order inside the process sequential too?

 

Thanks!

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4 Replies
Historian
Historian
83 Views
Registered: ‎01-23-2009

Re: Variable assignment inside a VHDL process in Synthesis

In general, if the behavior in simulation (i.e. the behavior described by the language) is deterministic, then synthesis will produce results that match the RTL description.

I the case of multiple assignments to the same variable in the same process, the behavior is deterministic - the last one wins. In this case, the synthesizer will create logic that results in the "final" value of the variable in all cases. It will not do it in any way similar to how it is done in the RTL description - it will basically make a truth table for all possible conditions that affect the variable a based on what the final value for the variable is, and then synthesize the truth table (so the "order of evaluation" doesn't exist once the design is synthesized).

BUT - what I said is only true if the behavior is deterministic. For example assigning a shared variable in two different processes will not result in a deterministic result (at least in Verilog - I am not as sure about VHDL), so the results from synthesis may not match the results in simulation. This would be considered a coding error.

Your code isn't complete - I presume the variables a and b are used in the process to determine the value to put into a flip-flop; you have this process described as a clocked process. If so, (and assuming the flip-flop is described by a signal), then this coding style is acceptable - using a variable as a temporary value for determining the next value of a signal (even if it is not a flip-flop) is relatively normal; some coding styles ask you to avoid it, but it is legal.

Avrum

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Scholar richardhead
Scholar
66 Views
Registered: ‎08-01-2012

Re: Variable assignment inside a VHDL process in Synthesis

I highly recommend you avoid using variables until you fully understand the consequences of using them. There is almost NOTHING in synthesisable VHDL that you need variables for. Everything you need can be done with signals, and signals are what are mostly used in VHDL to infer hardware. So get familiar using signals first. 

For example assigning a shared variable in two different processes will not result in a deterministic result

Only if you attempted to assign the signals in the same delta. But you should get a multiple driver error on synthesis. You really shouldnt be using shared variables in VHDL at all though, and be sticking with signals.

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Mentor hgleamon1
Mentor
48 Views
Registered: ‎11-14-2011

Re: Variable assignment inside a VHDL process in Synthesis

 

You really shouldnt be using shared variables in VHDL at all though

How does one otherwise infer a true DPRAM without using a shared variable?

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Scholar richardhead
Scholar
34 Views
Registered: ‎08-01-2012

Re: Variable assignment inside a VHDL process in Synthesis

@hgleamon1

You can quite happily use a signal.

UNLESS you need write before read behaviour. This is the ONLY reason to use a shared variable (which technically is illegal in VHDL 2002).

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