12-05-2018 06:39 PM
I'm a newbie in VHDL design. I have a doubt regarding different assignations to the same variable inside a process in a post-synthesized design.
For example the next code snippet:
--previous code p1 : process (clk,reset) variable a : std_logic; variable b : std_logic; begin a := '1' --some code here that modifies b variable if ( b = '1') then a := '0'; end if; end process; --the code goes on
Can it be assured that during execution in FPGA, if b is '1', a always will be '0'. In other words, I know that during simulation all statements inside a process are executed sequentially, but can we say the same in relation to a synthesized design? Is the execution order inside the process sequential too?
12-05-2018 08:33 PM
In general, if the behavior in simulation (i.e. the behavior described by the language) is deterministic, then synthesis will produce results that match the RTL description.
I the case of multiple assignments to the same variable in the same process, the behavior is deterministic - the last one wins. In this case, the synthesizer will create logic that results in the "final" value of the variable in all cases. It will not do it in any way similar to how it is done in the RTL description - it will basically make a truth table for all possible conditions that affect the variable a based on what the final value for the variable is, and then synthesize the truth table (so the "order of evaluation" doesn't exist once the design is synthesized).
BUT - what I said is only true if the behavior is deterministic. For example assigning a shared variable in two different processes will not result in a deterministic result (at least in Verilog - I am not as sure about VHDL), so the results from synthesis may not match the results in simulation. This would be considered a coding error.
Your code isn't complete - I presume the variables a and b are used in the process to determine the value to put into a flip-flop; you have this process described as a clocked process. If so, (and assuming the flip-flop is described by a signal), then this coding style is acceptable - using a variable as a temporary value for determining the next value of a signal (even if it is not a flip-flop) is relatively normal; some coding styles ask you to avoid it, but it is legal.
12-06-2018 02:36 AM
I highly recommend you avoid using variables until you fully understand the consequences of using them. There is almost NOTHING in synthesisable VHDL that you need variables for. Everything you need can be done with signals, and signals are what are mostly used in VHDL to infer hardware. So get familiar using signals first.
For example assigning a shared variable in two different processes will not result in a deterministic result
Only if you attempted to assign the signals in the same delta. But you should get a multiple driver error on synthesis. You really shouldnt be using shared variables in VHDL at all though, and be sticking with signals.
12-06-2018 09:16 PM
You really shouldnt be using shared variables in VHDL at all though
How does one otherwise infer a true DPRAM without using a shared variable?
12-07-2018 01:56 AM