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Visitor jaehyuk
Visitor
15,412 Views
Registered: ‎01-01-2018

Vector/Array declaration in Verilog (reg [7:0] var, reg[0:7] var2 how they are different?)

I would like to ask about array declaration.

As far as I know, when we declare vector or array in Verilog,

we use the syntax like

 

reg [7:0] reg1;

reg [0:7] reg2;

 

reg [7:0] array1 [0:2];

reg [7:0] array2 [2:0];

 

I've tried to understand how they are different in accessing the variable and storing it in the flop.

From this blog (http://www.asic-world.com/verilog/verilog_one_day1.html)

It seems that endianness is changed depending on the position of the larger value.

And I wrote the code (https://pastebin.com/zBveiYxU) to test how they are different

when they are stored in the flop and how they can be referenced in a different way.

 

This is the result that I got from the above code. 

 

# run 1000ns
Test1====================
array_msb = 10110000
array_msb[0] = 0
array_lsb = 10100000
array_lsb[0] = 1

Test2================
array1[0]: 10000000
array1[1]: 01000000
array1[2]: 00100000
====================
array2[0]: 10000000
array2[1]: 01000000
array2[2]: 00100000

 

It seems that vector array is stored in the little-endian fashion regardless of [7:0] and [0:7]

as shown by the printed messages array_msb = 10110000 and array_lsb = 10100000 

(Although it could be different when the code is synthesized to the gate).

However, it seems that each element can be referenced in different endianness depending on the declaration

shown by the array_msb[0] = 0 and array_lsb[0] = 1 even though we assign the same value.

 

Interestingly, it doesn't follow the above rule when we declare multi-dimensional arrays.

I predicted the result will be like below, but not a true. 

array1[0]: 10000000
array1[1]: 01000000
array1[2]: 00100000
====================
array2[0]: 00100000
array2[1]: 01000000
array2[2]: 10000000

 

Could anyone please explain what is the difference between these declarations? 

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4 Replies
Explorer
Explorer
15,345 Views
Registered: ‎09-07-2011

Re: Vector/Array declaration in Verilog (reg [7:0] var, reg[0:7] var2 how they are different?)

There's no reordering, or endianess behind the scenes.   The bits are written where you write them.

 

Vectors :    

 

reg [ LEFT_BIT_INDEX : RIGHT_BIT_INDEX ]  my_vector;

 

Whether LEFT > RIGHT, or LEFT < RIGHT does not change the bit order:

 

Arrays : 

 

reg [ L : R ]    my_array [ FIRST_INDEX : LAST_INDEX]

 

Whether FIRST < LAST or FIRST > LAST, does not change the element order.

 

Example:  

 

// system verilog

module top;

reg [7:0] array1 [0:2] = { 8'haa, 8'hbb, 8'hcc }; 
reg [7:0] array2 [2:0] = { 8'haa, 8'hbb, 8'hcc }; 

initial begin
	#1;
	assert (array1    == array2);
	assert (array1[0] == array2[2]); // FIRST equals FIRST
	assert (array1[0] != array2[0]); // FIRST not equal LAST
end 

endmodule

 

 

 

 

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Visitor jaehyuk
Visitor
15,334 Views
Registered: ‎01-01-2018

Re: Vector/Array declaration in Verilog (reg [7:0] var, reg[0:7] var2 how they are different?)

Thanks for an answer, I've tried to test your code, but I faced the error "cannot assign a packed type to an unpacked type".

 

Is the assignment like 

 

reg [7:0] array2 [0:2] = '{ 8'haa, 8'hbb, 8'hcc };

 

not allowed in the Verilog language? 

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Explorer
Explorer
15,306 Views
Registered: ‎09-07-2011

Re: Vector/Array declaration in Verilog (reg [7:0] var, reg[0:7] var2 how they are different?)

Well, the example should work with system verilog turned on.  (At least my Modelsim was OK with it).

 

That said, there's also the concept of packed and unpacked arrays.  There's syntax for packed or unpacked array literals, but I don't recall which is which without looking it up.  

 

Might need some help from a system verilog person .. anyone out there :)?

 

I used  array1 = { a , b , c} in my example and you used array1 = ' { a , b , c } with the tick.   

 

 

 

 

 

 

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Scholar markcurry
Scholar
15,296 Views
Registered: ‎09-16-2009

Re: Vector/Array declaration in Verilog (reg [7:0] var, reg[0:7] var2 how they are different?)


@geoffbarnes wrote:

Well, the example should work with system verilog turned on.  (At least my Modelsim was OK with it).

 

That said, there's also the concept of packed and unpacked arrays.  There's syntax for packed or unpacked array literals, but I don't recall which is which without looking it up.  

 

Might need some help from a system verilog person .. anyone out there :)?

 

I used  array1 = { a , b , c} in my example and you used array1 = ' { a , b , c } with the tick.   

 

 


 

This get's into some rather detailed areas of the SystemVerilog specification.  See 10.10 "Unpacked Array Concatenation" of the IEEE 1800-2009 for all the gory details.

 

But the short answer - either form of the literal should work (i.e. with or without the casting tick ' )

 

But you must have SystemVerilog mode turned on in your tool for either case to work.

 

Regards,

 

Mark