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Adventurer
Adventurer
734 Views

Verilog Coding Question

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Hello All,

I saw an if statement in Verilog code which looks like this,

 

      if (tx_ready & |state)

 

In the above tx_ready is a wire, and state is reg[1:0].

 

I don't understand the meaning of & |state

 

any idea what that would be?

 

Thanks,

Manoj

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1 Solution

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Moderator
Moderator
1,252 Views

Re: Verilog Coding Question

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Hi @manoj_xilinx,

As Rohit pointed out there is no &| operator in verilog.

Now, if we consider the statement, tx_ready & |state, it performs bit wise or operation for reg state (i.e., it coverts 2 bits of state to 1 bit) and then it performs Bit wise and operation with tx_ready.

 

Thanks & Regards,
A.Shameer.

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Moderator
Moderator
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Re: Verilog Coding Question

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Hi @manoj_xilinx

 

| is bitwise OR operator and & is bitwise AND operator. I don't think there is any operator '& | ' in verilog because ultimately bit wise or operation and bitwise AND operation has to be happened between two operands. Can you please share the code to investigate this?

Also refer the link below,page 33:

http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf

 

Regards

Rohit

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Regards
Rohit
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Moderator
Moderator
1,253 Views

Re: Verilog Coding Question

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Hi @manoj_xilinx,

As Rohit pointed out there is no &| operator in verilog.

Now, if we consider the statement, tx_ready & |state, it performs bit wise or operation for reg state (i.e., it coverts 2 bits of state to 1 bit) and then it performs Bit wise and operation with tx_ready.

 

Thanks & Regards,
A.Shameer.

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Adventurer
Adventurer
707 Views

Re: Verilog Coding Question

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Thank you, Rohit, and Shameer.Got cleared!

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