UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

Verilog Coding Question

Accepted Solution Solved
Adventurer
Posts: 93
Registered: ‎11-22-2016
Accepted Solution

Verilog Coding Question

Hello All,

I saw an if statement in Verilog code which looks like this,

 

      if (tx_ready & |state)

 

In the above tx_ready is a wire, and state is reg[1:0].

 

I don't understand the meaning of & |state

 

any idea what that would be?

 

Thanks,

Manoj


Accepted Solutions
Moderator
Posts: 207
Registered: ‎05-31-2017

Re: Verilog Coding Question

Hi @manoj_xilinx,

As Rohit pointed out there is no &| operator in verilog.

Now, if we consider the statement, tx_ready & |state, it performs bit wise or operation for reg state (i.e., it coverts 2 bits of state to 1 bit) and then it performs Bit wise and operation with tx_ready.

 

Thanks & Regards,
A.Shameer.

View solution in original post


All Replies
Moderator
Posts: 909
Registered: ‎09-15-2016

Re: Verilog Coding Question

Hi @manoj_xilinx

 

| is bitwise OR operator and & is bitwise AND operator. I don't think there is any operator '& | ' in verilog because ultimately bit wise or operation and bitwise AND operation has to be happened between two operands. Can you please share the code to investigate this?

Also refer the link below,page 33:

http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Moderator
Posts: 207
Registered: ‎05-31-2017

Re: Verilog Coding Question

Hi @manoj_xilinx,

As Rohit pointed out there is no &| operator in verilog.

Now, if we consider the statement, tx_ready & |state, it performs bit wise or operation for reg state (i.e., it coverts 2 bits of state to 1 bit) and then it performs Bit wise and operation with tx_ready.

 

Thanks & Regards,
A.Shameer.

Highlighted
Adventurer
Posts: 93
Registered: ‎11-22-2016

Re: Verilog Coding Question

Thank you, Rohit, and Shameer.Got cleared!