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fpga_freak
Observer
Observer
9,537 Views
Registered: ‎11-01-2007

Verilog Generate

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Hi All,

  Does verilog allows to use generate statements inside another generate statement.
I have a requirement as shon below,

 generate if (A >1) // A is a top level generic
     generate  for (i=0; i<10; i=i+1)
     begin : START
          logic.....
     end
     endgenerate
endgenerate

The above gives errors while compiling. Any other option to use generate inside another generate.

regards,
freak
1 Solution

Accepted Solutions
gszakacs
Instructor
Instructor
11,363 Views
Registered: ‎08-14-2007

according to the syntax from the manual, you should be able to have a loop within

a conditional like:

 

 generate

   if (A >1) // A is a top level generic

   begin : OUTER
     for (i=0; i<10; i=i+1)
     begin : INNER

         logic.....
     end
   end

endgenerate

 

Note that the keywords generate and endgenerate only appear once.

 

HTH,

Gabor

-- Gabor

View solution in original post

3 Replies
gszakacs
Instructor
Instructor
11,364 Views
Registered: ‎08-14-2007

according to the syntax from the manual, you should be able to have a loop within

a conditional like:

 

 generate

   if (A >1) // A is a top level generic

   begin : OUTER
     for (i=0; i<10; i=i+1)
     begin : INNER

         logic.....
     end
   end

endgenerate

 

Note that the keywords generate and endgenerate only appear once.

 

HTH,

Gabor

-- Gabor

View solution in original post

fpga_freak
Observer
Observer
9,507 Views
Registered: ‎11-01-2007

Thanx a lot Gabor. This really helped me.

 

I have one more query.

 

What the difference between including a file below module port declaration and after port declaration.

An example is shown below,

 

 

'include File_pkg.v

  module ( input a,

                 output b);

 

   logic---

 

 

Now the same code can also be doen as shown below,

 

  module ( input a,

                 output b);

 

'include File_pkg.v

 

  logic----

 

Please share your thought.

 

regards,

freak

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gszakacs
Instructor
Instructor
9,497 Views
Registered: ‎08-14-2007

`include just reads the contents of the include file and places it in line where the `include

directive is.  It's the equivalent of copying the file contents and pasting them into your

.v file at the same location as the directive.  So anything included outside the module

definition would be outside the scope of that module.  Usually include files are used

for parameters or `defines.  The `defines are global, so they could go outside the

module definition.  Parameters would need to go inside a module, as would any behavioral code.

But there's also no reason you couldn't have complete modules in the included file

and then include it outside the module definition.  This is one way to ensure the

compilation order, however you're generally better off letting the tools decide that

and working with multiple source files instead of included modules.

 

regards,

Gabor

-- Gabor