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kenryan2
Explorer
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Registered: ‎04-22-2015

Verilog implicit nets

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Is there a way to tell Vivado synthesis (2016.2) to refuse to accept an implicitly declared wire or reg?  I keep getting bit by a typo in a name happily synthesizing into a ground rather than getting flagged as an error.

 

Thanks

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tud_hartmann
Adventurer
Adventurer
9,652 Views
Registered: ‎02-24-2012

Hi @kenryan2,

 

`default_nettype directive is what you are looking for. Simply write

 

`default_nettype none

 

at the beginning of your Verilog file, but don't forget to reset it at the end:

 

`default_nettype wire

 

Best Regards,

 

Stephan

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tud_hartmann
Adventurer
Adventurer
9,653 Views
Registered: ‎02-24-2012

Hi @kenryan2,

 

`default_nettype directive is what you are looking for. Simply write

 

`default_nettype none

 

at the beginning of your Verilog file, but don't forget to reset it at the end:

 

`default_nettype wire

 

Best Regards,

 

Stephan

View solution in original post

kenryan2
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5,449 Views
Registered: ‎04-22-2015

Ah, thank you!

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