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Visitor
Visitor
9,585 Views
Registered: ‎10-26-2015

Verilog question about two clk input for ise 14.7

Hi, there

 

We wrtie a verilog code based on CB4CLE function, but i always get Gated clock warning, wondering how could i avoid this kind warning :

 

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_588/XLXI_322/XLXI_99/LC_Q2_AND_6_o is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_588/XLXI_322/XLXI_99/LC_Q0_AND_2_o is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_588/XLXI_322/XLXI_99/LC_Q1_AND_4_o is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_588/XLXI_322/XLXI_99/LC_Q3_AND_8_o is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.

 

 

here is code:

module CB4CLE_MP(Q0, Q1, Q2, Q3, LEN, CEN, LC, C, CLR, D0, D1, D2, D3);


   output             Q0;
   output             Q1;
   output             Q2;
   output             Q3;

   
   input       LEN;
   input       LC;
   input       CEN;
	
   input       C;
   input       CLR;
	
   input              D0;
   input              D1;
   input              D2;
   input              D3;

   
   reg                Q0;
   reg                Q1;
   reg                Q2;
   reg                Q3;
   
   always @( posedge LC or posedge C or posedge CLR)
     begin
		if (CLR)
		{Q3, Q2, Q1, Q0} <= 4'b0000;
		else
		begin
		
		if (LC)
	          begin
		   if (LEN)
                      {Q3, Q2, Q1, Q0} <= {D3, D2, D1, D0};
	          end
		else
		 begin
			if (CEN)
			{Q3, Q2, Q1,Q0} <= {Q3, Q2, Q1,Q0} + 1;
			end
		 end
		
    end		
			
endmodule
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Guide
Guide
9,578 Views
Registered: ‎01-23-2009

As you have coded it, you have asked for an asynchronous clear and an asynchronous load. No physical resource in an FPGA can do this.

 

If you are really trying to code the CB4CLE, the load is supposed to be synchronous - you need to remove the "posedge LC" from the always @(...)

 

Avrum

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Moderator
Moderator
9,557 Views
Registered: ‎06-24-2015

Hi @kaiyangsun,

 

Refer to this link:
http://www.xilinx.com/support/answers/46375.html

 

 

Thanks,
Nupur
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