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mbrejza
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Registered: ‎11-22-2017

Verilog synthesis design using multiple libraries

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I've been trying to synthesize a design which relies on a couple of our existing projects. Each of these projects uses modules from a 'common rtl' repository, which contains modules such as FIFOs and AXI components. However, each project has been verified against a different version of of the common repository, so when compiling the overall design, each previously verified project will need to use the version of the common repository with which they were verified. This means that I am trying to synthesize a design which has duplicate modules.

With other tools I can simply compile each set of files into different libraries to keep duplicates separate, however I am struggling with vivado. I have attached a basic example.

When giving this example to 2019.1, it only uses one of the duplicate files, even when each are placed into different libraries

mbrejza_0-1615400365862.png

However 2020.2 looks more promising, but does something different. When compiling, the top level that uses the xil_default_lib cannot use files that sit in different libraries

mbrejza_1-1615400566787.png

I also tried the config/endconfig constructs, but it seems these are not supported.

If this approach is not going to work, is there an alternative approach?

Thanks in advance.

 

 

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aher
Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014

Hi @mbrejza 

Currently Vivado parser (in project mode) has very limited support for verilog library and config usage.
However, you can use this feature in tcl/batch mode. I will file an enhancement to make this availble in project mode as well in future release.

I have attached your project in tcl mode with slight modification in lib.sv- run user_synth.tcl. Looks like there is some issue when top level module description has to be taken from xil_defaultlib. I have used library work as a workaround for now. We are investigating this issue further.

Let me know if you have any inputs.

-Shreyas

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aher
Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014

Hi @mbrejza 

Currently Vivado parser (in project mode) has very limited support for verilog library and config usage.
However, you can use this feature in tcl/batch mode. I will file an enhancement to make this availble in project mode as well in future release.

I have attached your project in tcl mode with slight modification in lib.sv- run user_synth.tcl. Looks like there is some issue when top level module description has to be taken from xil_defaultlib. I have used library work as a workaround for now. We are investigating this issue further.

Let me know if you have any inputs.

-Shreyas

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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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aher
Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014

Hi @mbrejza 

 

An update regarding xil_defaultlib-

If top module is compiled into default library or xil_defaultlib, you need not explicitly mention it in config definition. In that case your configuration can look like-

config cfg2;

design top;

instance top.u_mod_a liblist liba;
instance top.u_mod_a.u_ram_module_a liblist liba;

instance top.u_mod_b liblist libb;
instance top.u_mod_b.u_ram_module_b liblist libb;

endconfig

 

Regards,

Shreyas

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mbrejza
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Registered: ‎11-22-2017

Thanks Shreyas,

I managed to get the example to compile in tcl batch mode using the commands you provided. However, I did not end up using the config/endconfig file - vivado did not want to use that as a top level (ERROR: [Synth 8-27] non module instantiation not support). The tcl I used in the end was:

read_verilog -sv -library liba ./lib1/module_a.sv
read_verilog -sv -library liba ./lib1/ram.sv
read_verilog -sv -library libb ./lib2/module_b.sv
read_verilog -sv -library libb ./lib2/ram.sv
read_verilog -sv -library work ./top.sv
synth_design -top top

 

One observation though - this flow does not support two different libraries both requiring the same package. For example:

# Compile the package twice into each library (doesnt work)
read_verilog -sv -library liba my_pkg.sv ;
read_verilog -sv -library libb my_pkg.sv ; # Gives warning about duplicate file: WARNING: [filemgmt 56-12] File 'my_pkg.sv' cannot be added to the project because it already exists in the project, skipping this file


# Compile two modules in two libraries that both need the same package
read_verilog -sv -library liba module_a.sv # requires my_pkg.sv
read_verilog -sv -library libb module_b.sv # requires my_pkg.sv, but it cannot be accessed: ERROR: [Synth 8-1031] my_pkg is not declared

Compiling my_pkg.sv to a default library does also not seem to work.

 

The package limitation is not an issue for our current project, but in future vivado versions it would be good to see this working.

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aher
Xilinx Employee
Xilinx Employee
861 Views
Registered: ‎07-21-2014

Hi @mbrejza 

1- Regarding error that you are facing when config is set as top-
When we are synthesizing top "module" set as top, how are you checking if submodule definitions are picked from intened libraries?
I am able to successfully run your project with cfg as top in vivado 2020.2. If possible, can you please post your synth.tcl and config definition, I will try to check if something is missing.

2- Regarding compileing package file into different libraries, we are investigating if this can be enhanced in the future release.

Regards,

Shreyas

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mbrejza
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Registered: ‎11-22-2017

Hi Shreyas,

Your original solution for config/endconfig does work in the end - I missed a line in lib.sv from your example. In particular, I copied your second example that was missing the "design work.top; default liblist work;" lines which was supposed to be used when the top module is in the default library, but I had compiled the top module into the work library.

Glad to hear the library support is being investigated.

Thanks.

 

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richardhead
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Registered: ‎08-01-2012

@aher 

Did you mean that you can use the feature in non-project mode? you can create either project or non-project mode projects using both tcl/batch modes of Vivado, and you can also open checkpoints from non-project mode in the GUI. Project/non-project mode is simply how the project is created and nothing to do with what mode vivado is run in.

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aher
Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014

Hi @richardhead 

 

With tcl/batch mode i mean both project and non-project flows when used in tcl/batch mode. The issue appears to be in GUI mode.

 

Regards,

Shreyas

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kalyana
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Registered: ‎03-19-2021

Hi Shreyas,

Is there any combination of the above that would work in tcl or batch mode, such that in the above example the file name and module name are the same. By this, I mean in the above example module_b would be renamed as module_a. Thereby there  would be 2x module_a's that would be compiled into 2x libraries (lib1 and lib2) and then linked at the top?

Thanks

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