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Visitor
Visitor
697 Views
Registered: ‎08-31-2019

Vhdl with VGA Controller

Good day,

I did it with Vga control, but I'm trying to create a color palette.I have encountered such an error. I don't understand how I'm making mistakes at replacements. Thanks for your help.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; 
use ieee.numeric_std.all;
--use IEEE.STD_logic_ARITH.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_signed.all;
 
entity VGA_Test is
    generic(RGBLength : integer := 1);
    port(Clk : in std_logic;                                    --Clk girişi
        R, G, B : out std_logic_vector(RGBLength - 1 downto 0);  --VGA R, G, B sinyalleri
        HSync, VSync : out std_logic);                           --VGA HSync, VSync sinyalleri
end VGA_Test;
 
architecture Behavioral of VGA_Test is
     
--VGA sürücü componenti    
component vga_pll
    generic(RGBLength : integer := 1);                               --R, G, B sinyallerinin genişliği
                                                                     --(Renk derinliği)
                                                                                           
    port(Clk : in std_logic;                                         --Clk girişi
     
        X, Y : out std_logic_vector(15 downto 0);                     --X,Y koordinatları
                                                                      --Bu sinyaller o an hangi pixelin DAC'ye
                                                                                          --gönderileceğini belirtir.
        Rin, Gin, Bin : in std_logic_vector(RGBLength - 1 downto 0);  --R, G, B bilgileri
                                                                      --Okunan X, Y sinyallerine göre istenen 
                                                                                          --RGB verisi bu sinyaller tarafında gönderilir.
         
                                                                      --Monitöre giden sinyaller
        R, G, B : out std_logic_vector(RGBLength - 1 downto 0);       --DAC'ye gönderilercek RGB sinyalleri
        HSync, VSync : out std_logic);                                --Yatay ve Dikey senkronizasyon sinyalleri
end component;    
 
 
    signal Xs, Ys : std_logic_vector(15 downto 0);
     
    signal X, Y : integer range 0 to 2**20-1;
    signal Rin, Gin, Bin : std_logic_vector(0 downto 0);
 
begin
 
    --Xs, Ys sinyalleri integer'a dönüştürülür
    X <= to_integer(unsigned(Xs));
    Y <= to_integer(unsigned(Ys));
 
    VGADriver : vga_pll
        generic map(1)
        port map(Clk => Clk, X => Xs , Y => Ys, Rin => Rin , Gin => Gin, Bin => Bin , R => R , G => G, B => B, HSync => HSync, VSync => VSync);
         
    process(X, Y)
    begin
         
        --Renk Paleti
        Bin(0) <= std_logic_vector(to_unsigned(X / 160, 3))(0);
        Gin(0) <= conv_std_logic_vector(to_unsigned(X / 160, 3))(1);
        Rin(0) <= conv_std_logic_vector(to_unsigned(X / 160, 3))(2);
                 
    end process;
         
end Behavioral;
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18 Replies
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Teacher
Teacher
695 Views
Registered: ‎07-09-2009

Re: Vhdl with VGA Controller

I agree,

thats a problem,

   can i suggest, may be not, may be so,  that you look at the hen book, and once the golden egg of understanding has been laid,

      then more scrambled not will be the results,

yoda him say,

 

 

 

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663 Views
Registered: ‎06-21-2017

Re: Vhdl with VGA Controller

What error are you seeing?  Did you simulate?

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Visitor
Visitor
617 Views
Registered: ‎08-31-2019

Re: Vhdl with VGA Controller

I'm sory. I forgot to write the error. Error related to variables.
WhatsApp Image 2019-10-10 at 11.49.02.jpeg

 

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602 Views
Registered: ‎06-21-2017

Re: Vhdl with VGA Controller

You don't need

 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_signed.all;

the numeric_std library includes everything you need for this code.  The synthesis tool does not know which definition of to_unsigned to use.

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Visitor
Visitor
596 Views
Registered: ‎08-31-2019

Re: Vhdl with VGA Controller

Thank you but again there is error. I write according to the rules but did not. I do not understand.image.png

 

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Teacher
Teacher
558 Views
Registered: ‎07-09-2009

Re: Vhdl with VGA Controller

sorry,

 

 

you hav emodified you rcode, and then shown us a little bit of it, and said there is an error,

  Can you post you rcode as an attatchment please,

  Im detecting your learning VHDL,

can I suggest you need a better book,

here are some ( IMHO ) usefull links,

http://www.bitweenie.com/listings/vhdl-type-conversion/

http://freerangefactory.org/

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar
Scholar
549 Views
Registered: ‎08-01-2012

Re: Vhdl with VGA Controller

@karahanli 

You have included numeric_std twice, importing all the types twice, making anything in them invisible.

You have also included std_logic_signed and unsigned, also making most of both libraries invisible (as they define the same functions on the same types)

 

Only include the library once. And preferably remove the std_logic_signed and unsigned pakcages (as they are not standard VHDL).

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Teacher
Teacher
516 Views
Registered: ‎07-09-2009

Re: Vhdl with VGA Controller

I did not relalise including the same library twice caused problems.

Th ecode does need some serious mentoring on it though

 

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Scholar
Scholar
508 Views
Registered: ‎08-01-2012

Re: Vhdl with VGA Controller

@drjohnsmith 

Neither did I - but given the OP has only posted this one code, I can only see that as the problem.

Unless they are compiling code that hasnt been posted, and has numeric_std and std_logic_arith included, which is the usual source of this error.

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484 Views
Registered: ‎06-21-2017

Re: Vhdl with VGA Controller

If you blow up the screenshot of the OP's last post, you see a different error "Cannot index the results of a type conversion." 

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464 Views
Registered: ‎06-21-2017

Re: Vhdl with VGA Controller

First, you have no variables in any of the code you posted.  You have signals.  They are very different.

I think you have X and Y declared as std_logic_vectors but you are trying to assign an integer to them.

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Teacher
Teacher
429 Views
Registered: ‎07-09-2009

Re: Vhdl with VGA Controller

can you post as an attatchment all your code and the test benche please, then we can advise
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar
Scholar
420 Views
Registered: ‎04-26-2015

Re: Vhdl with VGA Controller

@karahanli I could be wrong, but I think you're doing three separate divide operations here too. Vivado knows how to do a divide, but you'd better be prepared for a very large and slow piece of hardware - dividing by anything other than a power of 2 is not easy.

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Visitor
Visitor
352 Views
Registered: ‎08-31-2019

Re: Vhdl with VGA Controller

Thanks for your help. but I still haven't solved the problem. I only use these libraries.
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_1164.ALL;

--Kütüphaneler
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; 
--use ieee.numeric_std.all;
--use IEEE.STD_logic_ARITH.all;
 --use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_signed.all;
 
entity VGA_Test is
    generic(RGBLength : integer := 1);
    port(Clk : in std_logic;                                    --Clk girişi
        R, G, B : out std_logic_vector(RGBLength - 1 downto 0);  --VGA R, G, B sinyalleri
        HSync, VSync : out std_logic);                           --VGA HSync, VSync sinyalleri
end VGA_Test;
 
architecture Behavioral of VGA_Test is
     
--VGA sürücü componenti    
component vga_pll
    generic(RGBLength : integer := 1);                               --R, G, B sinyallerinin genişliği
                                                                     --(Renk derinliği)
                                                                                           
    port(Clk : in std_logic;                                         --Clk girişi
     
        X, Y : out std_logic_vector(15 downto 0);                     --X,Y koordinatları
                                                                      --Bu sinyaller o an hangi pixelin DAC'ye
                                                                                          --gönderileceğini belirtir.
        Rin, Gin, Bin : in std_logic_vector(RGBLength - 1 downto 0);  --R, G, B bilgileri
                                                                      --Okunan X, Y sinyallerine göre istenen 
                                                                                          --RGB verisi bu sinyaller tarafında gönderilir.
         
                                                                      --Monitöre giden sinyaller
        R, G, B : out std_logic_vector(RGBLength - 1 downto 0);       --DAC'ye gönderilercek RGB sinyalleri
        HSync, VSync : out std_logic);                                --Yatay ve Dikey senkronizasyon sinyalleri
end component;    
 
 
    signal Xs, Ys : std_logic_vector(15 downto 0);
     
    signal X, Y : integer range 0 to 2**20-1;
    signal Rin, Gin, Bin : std_logic_vector(0 downto 0);
 
begin
 
    --Xs, Ys sinyalleri integer'a dönüştürülür
    X <= to_integer(unsigned(Xs));
    Y <= to_integer(unsigned(Ys));
 
    VGADriver : vga_pll
        generic map(1)
        port map(Clk => Clk, X => Xs , Y => Ys, Rin => Rin , Gin => Gin, Bin => Bin , R => R , G => G, B => B, HSync => HSync, VSync => VSync);
         
    process(X, Y)
    begin
         
        --Renk Paleti
        Bin(0) <= std_logic_vector(to_unsigned(X / 160, 3))(0);
        Gin(0) <= std_logic_vector(to_unsigned(X / 160, 3))(1);
        Rin(0) <= std_logic_vector(to_unsigned(X / 160, 3))(2);
                 
    end process;
         
end Behavioral;
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Scholar
Scholar
339 Views
Registered: ‎08-01-2012

Re: Vhdl with VGA Controller

Please report the errors you get now.

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Visitor
Visitor
334 Views
Registered: ‎08-31-2019

Re: Vhdl with VGA Controller

Same errors.

Capture.PNG

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Scholar
Scholar
325 Views
Registered: ‎08-01-2012

Re: Vhdl with VGA Controller

So the error is obvious, you cannot slice a type conversion. So you'll need to assign it to a temporary signal then slice that.

 

Highlighted
Teacher
Teacher
301 Views
Registered: ‎07-09-2009

Re: Vhdl with VGA Controller

How are u expecting the hardware to implement X/160 ? 

Draw out the logic your expecting would be informative.

I'd suggest, as u only want 3 bits out, that u construct either a 8 level case statement , or a constant look up table . 

 

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