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Adventurer
Adventurer
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Registered: ‎01-19-2018

Video Processing Subsystem

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ERROR: [Synth 8-439] module 'bd_5c69_csc_0_v_csc' not found [d:/v_hdmi_rx_ss_0_ex -- VPSs/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/bd_0/ip/ip_0/synth/bd_5c69_csc_0.v:185]
    Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32'sb00000000000000000000000000001000
    Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32'sb00000000000000000000000000100000
ERROR: [Synth 8-6156] failed synthesizing module 'bd_5c69_csc_0' [d://v_hdmi_rx_ss_0_ex - VPSs/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/bd_0/ip/ip_0/synth/bd_5c69_csc_0.v:57]
---------------------------------------------------------------------------------

 

Windows 10
Vivado 2018.2

What is the reason for not synthesizable Video Sub System IP, that is integrated in the system design.


Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @daram123,

 

I believe I know what is the issue. In your initial project you have spaces characters. Vivado HLS will not like that at all.

 

In the packages project, the spaces are gone from the path thus you faced no issue. You should always avoid using spaces in your path, prefer underscores.

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎01-16-2013

@daram123

 

Try resetting BD output products and regenerate them again. 

 

--Syed

 

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Adventurer
Adventurer
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Registered: ‎01-19-2018

All goes through except Video Processing SS IP.`

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎01-16-2013

@daram123

 

Try recustomizng the VSS IP and check. I suspect this to be an intermittent issue 

Can you share the vivado project to debug the issue?

 

--Syed

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @daram123,

 

Are you trying to synthesize the BD in non-project mode?

Please check the link https://www.xilinx.com/support/answers/70400.html

 

Thanks,

Raj Singh.

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Adventurer
Adventurer
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Registered: ‎01-19-2018

It is in Project mode. I reset and generate it  is showing the same result.


Regards,
Prasanna Daram

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Adventurer
Adventurer
2,742 Views
Registered: ‎01-19-2018

Project is not uploading.. is there a specific way to send you prj.


Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎01-16-2013

@daram123

 

I have sent you a private message from ezmove. Please upload the archive project from ezmove and send it back to us.

 

--Syed

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Adventurer
Adventurer
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Registered: ‎01-19-2018

Yeah It will whiz you in aminute.

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @daram123,

 

Few ideas:

  • Check the vivado_hls.log file under project.runs/...csc_synth_1. It should contain the error
  • If you do not have any error, try to use the TPG license

 

My guess is that your path is too long if you are using windows. This will be indicated by the vivado_hls.log

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎01-19-2018

ViVADO_HLS.log is only found under TPG IP. I didnt notice the hls.log for Video Processing SubSystem_synth1.
Synthesis has not generated any files under /...csc_synth_1. I tried re generating products in a new project and still its same.

Regards,
Prasanna Daram

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Voyager
Voyager
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Registered: ‎05-30-2017

Hi @daram123,

I had an error very similar to you and @florentw helped me to solve it as you can see here:

https://forums.xilinx.com/t5/Video/VPSS-2-0-doesn-t-syntetize/m-p/886118#M21624

My problem was that I enabled beta devices in init.tcl and beta devices are not supported by HLS.

I hope that this could help.

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Adventurer
Adventurer
2,716 Views
Registered: ‎01-19-2018

@pierlumi neither have

init.tcl

 Or have any vivado_init.tcl. in /...scripts

What i can do ?

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Moderator
Moderator
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Registered: ‎01-16-2013

@daram123

 

I do not have win10 so I have asked my colleague to run synthesis who has win10. I will get back to you on this. 

On Linux OS, I reset and regenerated the output products using "OOC per BD". The OOC run and main top module synthesis run completed successfully without any error message. 

Capture.JPG

 

Can you try the same on your machine? 

 

--Syed

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Voyager
Voyager
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Registered: ‎05-30-2017

@daram123,

if you are not using init.tcl or vivado_init.tcl the problem seems not to be what I suggested you. Did you try shortening path for example C:/x as suggested by @florentw?

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Adventurer
Adventurer
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Registered: ‎01-19-2018

@pierlum Yes.

Now I have initialzed to run out of context per block design.

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎09-15-2016

Hi @daram123,

 

I was just checking the files received from @syedz and synthesis does not error out for this design in Win10 2018.2. The only thing done was regenerating the IPs with OOC per IP.

 

Thanks

Prathik

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Adventurer
Adventurer
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Registered: ‎01-19-2018

@syedz@prathikm

 

Out of context per block has these messages.

 

 

ERROR: [Synth 8-439] module 'bd_5c69_csc_0_v_csc' not found [d:/v_hdmi_rx_ss_0_ex - vpss/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/bd_0/ip/ip_0/synth/bd_5c69_csc_0.v:185]
    Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32'sb00000000000000000000000000001000
    Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32'sb00000000000000000000000000100000
ERROR: [Synth 8-6156] failed synthesizing module 'bd_5c69_csc_0' [d:/v_hdmi_rx_ss_0_ex - vpss/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/bd_0/ip/ip_0/synth/bd_5c69_csc_0.v:57]
ERROR: [Synth 8-6156] failed synthesizing module 'bd_5c69' [d:/v_hdmi_rx_ss_0_ex - vpss/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/bd_0/synth/bd_5c69.v:10]
ERROR: [Synth 8-6156] failed synthesizing module 'exdes_v_proc_ss_0_0' [d:/v_hdmi_rx_ss_0_ex - vpss/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_proc_ss_0_0/synth/exdes_v_proc_ss_0_0.v:58]
ERROR: [Synth 8-6156] failed synthesizing module 'exdes' [D:/v_hdmi_rx_ss_0_ex - vpss/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/synth/exdes.v:393]
---------------

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎01-16-2013

@daram123

 

Do you have the license of the IP which you are using?

Run "report_ip_status -file ip_status.rpt" command and share the generated ip_status.rpt file.

Also run the following command from Vivado TCL console to generate xinfo.txt

report_environment -file xinfo.txt

 

After running the command just type “pwd” this will show you the path where the xinfo.txt and ip_status.rpt file is generated. You can browse to that path and find the files.

 

--Syed

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Adventurer
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Registered: ‎01-19-2018

These are the files.


Regards,
Prasanna Daram

VsppIP.JPG
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Moderator
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@daram123

 

I have verified the xinfo and it looks you have valid purchase and HW eval license of the IP in the design. 

Can you recreate the project at the different location (smaller dir path)and check? My colleague @prathikm has tested the design on Win10 os and it has synthesized successfully. 

 

Also Try clearing the cache of the IP. Please check this thread: 

https://forums.xilinx.com/t5/Installation-and-Licensing/Fail-to-generate-bitstream-with-Harware-evaluation-licence/m-p/892218#M23519

 

--Syed

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Adventurer
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Registered: ‎01-19-2018

Aila the archived project synthesized succesfuly.

 


got the bitstream. thank you

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @daram123,

 

I believe I know what is the issue. In your initial project you have spaces characters. Vivado HLS will not like that at all.

 

In the packages project, the spaces are gone from the path thus you faced no issue. You should always avoid using spaces in your path, prefer underscores.

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Explorer
Explorer
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Registered: ‎08-31-2016

@daram123

How did you solve this?

Vinay Shenoy
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @vinay_shenoy,

He replaced the space characters from his path to underscores


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
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Registered: ‎01-19-2018

@vinay_shenoyI archived Project from file->Project->archive.

Regards,
Prasanna Daram

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Explorer
Explorer
1,758 Views
Registered: ‎08-31-2016

Hi @daram123

Do you mean that you've just achieved the project and then recompiled it to solve this issue?

Regards,

Vinay

Vinay Shenoy
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Adventurer
Adventurer
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Registered: ‎01-19-2018
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