Virtex5 compile error - HDLParser: 3305: The actual value (Attribute name) assosiated with a generic must be a globally static expression

[s-stevanovic]

Hi all,

I'm trying to synthesize VHDL based project to Virtex5. However I have 2 problems which I don't fully understand. When I say fully it means that I've already looked for an answers at the internet and also on Xilinx forums and I have a clue of what might be the issue. So here it goes.

The code looks something like this:

1. inside a record I have some signals defined. And among others I have:

type memory_type is record

addr : std_logic_vector (31 downto 0);

end record;

2. In architecture part I'm instantiating the some logic like:

sram_based : IF SRAMBASED generate

u_addr : address generic map (comb.addr'length)

port map (clk, comb.addr, reg.addr);

end generate;

3. SRAMBASED is defined as:

constant SRAMBASED : boolean := false;

I)

Now the first problem is HDLParser: 3305: The actual value (Attribute name) assosiated with a generic must be a globally static expression pointing to u_addr instance. As I wrote above I've searched through the net and found that probably 'lenght (as being an operator) cannot be used here like this, but I'm still not sure is this really an issue.

II)

Why does the XST checks the code under generate even if SRAMBASED is set to false? This one is a mystery to me.

I would appreciate any help. Thanks in advance

Regards,

Stevan

[anusheel]

@s-stevanovic

Did you try using new_parser for XST synthesis?

I don't see any reason for an error based on the provided description, can you attach the RTL file here?

Thanks,
Anusheel
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[s-stevanovic]

Hi anusheel,

Thanks for answering. I forgot to mention that I'm using ISE 14.7, so I don't think that there is newer parser. Right? Is this what you were referring to when you wrote "new_parser "? Regarding the RTL it is not possible for me to upload files. But even if I could, then I would need to attach several files. The parameter (constant) declaration is in one file and constructed as a package. Similar for other parts of RTL ... Could this be an issue? The XST is at best a little bit strange when VHDL is used.

Regards,
Stevan

[s-stevanovic]

@anusheel

I've just typed a dummy code which should illustrate the problem. I'm not sure if it will compile now (tools where I already checked are inside nomachine) but as far as I've checked the code it should compile. I cannot see what is not static in the code so to me it looks like a bug in XST.  If you try to compile this you will get the mentioned error.

Regards,
Stevan

[gszakacs · Accepted solution]

I tried your code in ISE 14.7 using both the old and new parser.  The old one gives the error you posted.  The new parser has a different error:

ERROR:HDLCompiler:432 - "C:\Projects\junkola\dummy\dummy.vhd" Line 5: Formal <width> has no actual or default value.

Perhaps that is a better clue to the issue.

[edit] I added a default value in line 5, and the "new parser" now compiles it without error.  However even with the default, the old parser still gives the original error.

As a side note, to enable use of the new parser for older parts like Virtex 5, you need to go into the "additional command line options" for synthesis and type in:

-use_new_parser yes

[s-stevanovic]

Hi gszakacs,

It seems that it worked on the real code as well. But now I have different errors I would need to fix. There is one more thing I wanted to ask. Why does Check Syntax option under Synthesis, once run, gives different results in compare to Synthesize? Probably the parser again. Actually if I run the Check Syntax on the top level file then I get the same original error "... must be a globally static ...". And with Synthesize run we are still no where near of synthesizing the actual code.

One more thing I didn't mention. The code is passing this stage (compile and elab + synthesis) 100 % for Stratix IV. So the VHDL code should be fine (at least the part without vendor specific IPs). It is just a matter of satisfying the XST which is to be honest becoming annoying.

[gszakacs]

"Check Syntax" only checks for errors in language structure.  It doesn't find things like undeclared variables or multi-driven nets.  Also it's likely that "Check Syntax" is still using code from the old parser.  I find that it has limited use, mostly when I bring in freshly written code and I want to check for glaring errors before taking the time to run a full synthesis.  I also typically only use it for individual modules rather than running it on the top level of the project.  I think this is one of those quirks of ISE you just have to learn to live with.  It's likely that Vivado does a better job with your code, but you'd need to upgrade to 7-series or newer parts to use it.  Vivado is still actively maintained and Xilinx listens to customers' bug fix requests.

[s-stevanovic]

@gszakacs @anusheel

Thanks very much for your help. Everything is clear now.

I thought that I can mark several answers as a solution but apparently not. gszakacs was the first one that I've clicked so anusheel sorry. You have already asked (or at least provided a hint) about new parser...

Kind regards,
Stevan