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Observer sjjma
Observer
6,943 Views
Registered: ‎05-16-2012

Vivado 14.2 No ram usage after successful synthesis

I used Vivado ip catalog to generate a simple dual port ram & instantiated it in my rtl.

Synthesis was successful & the LUT count looks right but the memory usage in the utilization report shows 0.

 

I'm doing the same thing as I did in ISE & ISE shows the ram. What's different about Vivado ?

Everything is regenerated in Vivado. Nothing from ISE.

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6 Replies
Xilinx Employee
Xilinx Employee
6,930 Views
Registered: ‎02-14-2014

Re: Vivado 14.2 No ram usage after successful synthesis

Hello,

Are there any related critical warnings shown by the tool during synthesis? Can you attach both Vivado synthesis report and Utilization report ?
Regards,
Ashish
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Observer sjjma
Observer
6,926 Views
Registered: ‎05-16-2012

Re: Vivado 14.2 No ram usage after successful synthesis

The reports + original source verilog are attached.  The ram is just a simple dual port with registered inputs & outputs and always enabled.

 

Strange, won't let me add attachment. Complains about content not matching type.

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Observer sjjma
Observer
6,922 Views
Registered: ‎05-16-2012

Re: Vivado 14.2 No ram usage after successful synthesis

module ram512x36_test ( wr, datain, clka, clkb, wradr, rdadr, dataout, datain2 );

input wr;
input [35:0] datain;
input [35:0] datain2;
input clka;
input clkb;
input [8:0] wradr;
input [8:0] rdadr ;
output [35:0] dataout ;

wire wr;
reg [35:0] datawr ;
wire [35:0] datain;
wire [35:0] datain2 ;
wire clka;
wire clkb;
wire [8:0] wradr;
wire [8:0] rdadr ;
wire [35:0] dataout ;

always @ (posedge clka )
datawr <= #1 datain + datain2 ;

ram512x36x rbits70( .wea( wr ), .dina( datawr ), .addra( wradr ) ,
.clka( clka ), .clkb( clkb ),
.addrb( rdadr ) , .doutb( dataout ) ) ;

endmodule

Here's the original source. Perhaps you can just run it.
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Observer sjjma
Observer
6,911 Views
Registered: ‎05-16-2012

Re: Vivado 14.2 No ram usage after successful synthesis

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Observer sjjma
Observer
6,910 Views
Registered: ‎05-16-2012

Re: Vivado 14.2 No ram usage after successful synthesis

It worked !!! **bleep**. This is really messed up.
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Xilinx Employee
Xilinx Employee
6,898 Views
Registered: ‎09-20-2012

Re: Vivado 14.2 No ram usage after successful synthesis

Hi,

As ooc is enabled for the ip, the top level synthesis report will not show the ip utilization.

Open synthesized design and run report_utilization command in tcl console to see the correct utilization.

Thanks,
Deepika.
Thanks,
Deepika.
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