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Visitor mythdraenor
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Registered: ‎03-20-2008

Vivado 2013.1 terminates without a meaningful message

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My current design targeting a Kintex-7 part causes Vivado 2013.1 to terminate the synthesis run without any error messages or other messages stating that it is complete.  The system running this process is a 64-bit linux OS with 16GB of RAM.  This exact design will build just fine for a Virtex-6 part using PlanAhead or XST.

 

There are no error messages or critical warnings in the design up until this point.  The synth process terminates immediately after it displays the FSM message you see below.

 

Is there a flag I can give to vivado for a better idea of what is going on when it terminates?  I have already tried "-verbose" which did not help.

 

:

:

INFO: [Synth 8-3537] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the inputs of the operator [...]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

INFO: [Synth 8-802] inferred FSM for state register '..._reg' in module '...'
[Mon May 13 15:48:00 2013] synth_1 finished
wait_on_run: Time (s): cpu = 00:05:36 ; elapsed = 00:05:47 . Memory (MB): peak = 2075.465 ; gain = 0.000

 

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Visitor mythdraenor
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Registered: ‎03-20-2008

Re: Vivado 2013.1 terminates without a meaningful message

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I have come to believe it does.  I took the last line in the log (reference to the FSM) and thought perhaps there is something happening during that step.  I have the default synthesis strategy for Vivado synthesis which sets -fsm_extraction to "auto".  I changed it to "off" and that allows the design to synthesize and implement (and ultimately is functional).

 

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Explorer
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Registered: ‎04-28-2013

Re: Vivado 2013.1 terminates without a meaningful message

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what's your detail synth_design options ?

nonsense
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Explorer
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Registered: ‎04-28-2013

Re: Vivado 2013.1 terminates without a meaningful message

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May be Vivado 2013.1 synthesis tool has BUG. I had meet a BUG that can't synthesis DW_bsh codes. You can locate the module that cause the INFO and use XST synthesis tool to synthesize the module to gate level . You can read the module of gate level format to your whole design in Vivado 2013.1 and resynthesizing again!

 

nonsense
Visitor mythdraenor
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Registered: ‎03-20-2008

Re: Vivado 2013.1 terminates without a meaningful message

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I have come to believe it does.  I took the last line in the log (reference to the FSM) and thought perhaps there is something happening during that step.  I have the default synthesis strategy for Vivado synthesis which sets -fsm_extraction to "auto".  I changed it to "off" and that allows the design to synthesize and implement (and ultimately is functional).

 

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9,207 Views
Registered: ‎07-26-2013

Re: Vivado 2013.1 terminates without a meaningful message

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I too face the same issue. Exactly the same set of messages followed by synthesis failure.

But turning fsm extraction to off hasnt resolved it. The last line of synthesis failure INFO: [Synth 8-802] inferred FSM for state register '..._reg' in module '...' did go off though by turning it off.

 

Now it fails with INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]

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Historian
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Registered: ‎02-25-2008

Re: Vivado 2013.1 terminates without a meaningful message

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@sachinb_smachines wrote:

I too face the same issue. Exactly the same set of messages followed by synthesis failure.

But turning fsm extraction to off hasnt resolved it. The last line of synthesis failure INFO: [Synth 8-802] inferred FSM for state register '..._reg' in module '...' did go off though by turning it off.

 

Now it fails with INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [...]


You don't say what language you're using.  A code snippet would really help.

 

My guess is that you're using Verilog and your operands and/or your result vectors do not have the same length.

 

In VHDL, the compiler will simply barf when the size of all operands and result are not the same. Verilog happily truncates and extends to fit whatever is necessary. Seems to me like this INFO (it's not a WARNING, it's certainly not an ERROR and it's not a failure because the process continues) is telling you that your vectors are being munged and the result might not be what you expect. 

----------------------------Yes, I do this for a living.
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Registered: ‎07-26-2013

Re: Vivado 2013.1 terminates without a meaningful message

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I am using Verilog with 2013.2 Vivado. The RTL file in question had some adders of the below type.

 

wire [15:0] a,b;

wire [16:0] c;

 

assign c = {1'b0,a} + {1'b0,b};

 

These types of assignments were giving that INFO Message. So i changed them to be simply c = a + b;  types and the INFO message went away. But the synthesis still keeps failing. This time with absolutely no information why it fails.

 

So the code changes were only to suppress the info message which probably were unrelated to the real cause of synthesis failure.

 

The last lines in the runme.log file is

Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:04:42 ; elapsed = 00:05:02 . Memory (MB): peak = 4469.562 ; gain = 4355.098
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Compilation : Time (s): cpu = 00:04:42 ; elapsed = 00:05:02 . Memory (MB): peak = 4469.562 ; gain = 4355.098
---------------------------------------------------------------------------------

Whle the hs_err_*.log file has

#
# An unexpected error has occurred (11)
#
Stack:
/lib64/libc.so.6(+0x32a60) [0x7f79eb8e3a60]
/tools/xilinx/Xilinx_Vivado_Lin_2013.2_0616_1/Vivado/2013.2/lib/lnx64.o/librdi_synth.so(DFNode::calcConstantMerge(UConst&, UHashMap<DFPin*, UConst*, DFPin*, UEKey<DFPin*> >&, bool)+0x175) [0x7f79cf1b7ef5]
/tools/xilinx/Xilinx_Vivado_Lin_2013.2_0616_1/Vivado/2013.2/lib/lnx64.o/librdi_synth.so(DFPin::calcConstantInt(UConst&, UHashMap<DFPin*, UConst*, DFPin*, UEKey<DFPin*> >&, bool)+0x133) [0x7f79cf1b7453]

So as of now the cause of synthesis failure is not clear.

 

Thanks.

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Scholar markcurry
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Registered: ‎09-16-2009

Re: Vivado 2013.1 terminates without a meaningful message

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That's perfectly valid verilog code, with explicity defined behaviour.  The synthesizer shouldn't barf in either case.  It also should not build sub-optimal code when you do the sign-extension as you've done.  That's perfectly legal and valid code. 

 

You should submit the testcase to Xilinx for them to take a look at.

 

Regards,

 

Mark

 

 

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Historian
Historian
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Registered: ‎02-25-2008

Re: Vivado 2013.1 terminates without a meaningful message

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sachinb_smachines wrote:

Whle the hs_err_*.log file has

#
# An unexpected error has occurred (11)
#
Stack:
/lib64/libc.so.6(+0x32a60) [0x7f79eb8e3a60]
/tools/xilinx/Xilinx_Vivado_Lin_2013.2_0616_1/Vivado/2013.2/lib/lnx64.o/librdi_synth.so(DFNode::calcConstantMerge(UConst&, UHashMap<DFPin*, UConst*, DFPin*, UEKey<DFPin*> >&, bool)+0x175) [0x7f79cf1b7ef5]
/tools/xilinx/Xilinx_Vivado_Lin_2013.2_0616_1/Vivado/2013.2/lib/lnx64.o/librdi_synth.so(DFPin::calcConstantInt(UConst&, UHashMap<DFPin*, UConst*, DFPin*, UEKey<DFPin*> >&, bool)+0x133) [0x7f79cf1b7453]

So as of now the cause of synthesis failure is not clear.

 

Thanks.


i agree with Mark; your Verilog is perfectly fine.

 

I think the Xilinx parser has a bug. Hopefully, one of the Xilinx reps will contact you about submitting a test case, unless you're still able to open WebCases.

----------------------------Yes, I do this for a living.
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Registered: ‎07-26-2013

Re: Vivado 2013.1 terminates without a meaningful message

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Hello,

  I am uploading the file which fails synthesis.

If anyone in Xilinx can synthesize the file and do a root cause analysis , it would be really great.It fails with Vivado 2013.2

 

One observation: The cause of failure could be related to statemachine. Because if the statemachine register is unused (in the always block below statemechine), synthesis passes.

 

Also may be unrelated but i get a following message as well

" unable to generate logic for unpartitioned construct node cust_pro_txdma.v:331"

Line 331 is  (txdma_pkt_type == 2'h1)

 

I wonder what could be the problem.

 

I will try uploading the RTL file for the adders as well which give thos INFO message.

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado 2013.1 terminates without a meaningful message

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Interestingly out of all the inputs only this txdma_pkt_type is declared wire. I wonder if anything changes if you remove the wire.
Also if you are talking about tpro_cstate, there maybe something to it that you are using it outside its case block. If you also ask the synthesis tool to do FSM extraction, this might cause problems for some synthesizers.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Registered: ‎07-26-2013

Re: Vivado 2013.1 terminates without a meaningful message

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Hi,

 Nothing significant about that input wire. After seeing the message i added it hoping to if fixes. Doesnt.

If the line 331 is replaced by line 330, the message goes off.I know it is strange!!!!

 

Regarding using the states outside the always block it is generated is perfectly normal , widely used thing.

 

Also the fsm_extraction also doenst have any impact. I have tried with keeping auto and it still fails.

 Infact the real bummer is ...i have another code which fails if fsm extraction is NOT off. So i have to keep it off.The third message in this thread discusses that issue as well.

 

Thats why i thought of uploading the code to see if someone in Xilinx could help.

 

Thanks,

Sachin

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Registered: ‎07-26-2013

Re: Vivado 2013.1 terminates without a meaningful message

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Hello,

  Can someone in xilinx please look at the code i uploaded. The code fails synthesis without any message/reason for failure?

 

Thanks,

SAchin

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Visitor ocaldwell
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Registered: ‎09-18-2013

Re: Vivado 2013.1 terminates without a meaningful message

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I believe I'm having the same problem....Vivado is crashing with 'Abnormal Program Termination (11)' after a similar series of INFO and WARNING messages.  I'm running batch mode compile on a Linux 64-bit machine, targeting the Kintex 7 410 part, latest Vivado 2014.2 version. 

 

Here are the compiler messages before the crash:

 

INFO: [Synth 8-3537] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the inputs of the operator [/home/otto/prj/DFE/code/fpga/clock_manager.v:123]
INFO: [Synth 8-3537] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the inputs of the operator [/home/otto/prj/DFE/code/fpga/clock_manager.v:301]
INFO: [Synth 8-3537] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the inputs of the operator [/home/otto/prj/DFE/code/fpga/clock_manager.v:385]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [/home/otto/prj/DFE/code/fpga/clock_manager.v:363]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [/home/otto/prj/DFE/code/fpga/clock_manager.v:358]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [/home/otto/prj/DFE/code/fpga/clock_manager.v:363]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [/home/otto/prj/DFE/code/fpga/clock_manager.v:358]
WARNING: [Synth 8-3936] Found unconnected internal register 'cs_result_i_reg' and it is trimmed from '48' to '32' bits. [/home/otto/prj/DFE/code/fpga/clock_manager.v:531

 

Abnormal program termination (11)

This happens after the message 'Finished RTL Optimization' step.


Any help would be greatly appreciated.

 

 

 

 

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Advisor evgenis1
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Registered: ‎12-03-2007

Re: Vivado 2013.1 terminates without a meaningful message

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I'm having a similar problem to the one described in the thread. There is a message "+ operator cannot be merged with + operator due to loss of accuracy". Using Vivado 2017.4, and valid SystemVerilog code that simulates correctly.

The only difference is a synthesis warning, not an error.

 

Thanks,

Evgeni

 

 

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