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Visitor willparker
Visitor
11,481 Views
Registered: ‎03-20-2014

Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

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Hello,

 

I am trying to synthesize a single VHDL file in Vivado 2013.4, but I get the following errors:

 

ERROR: [Synth 8-1031] std_logic is not declared [C:/Users/willpark/xilinx_tests/project1.vhd:110]
ERROR: [Synth 8-1031] std_logic_vector is not declared [C:/Users/willpark/xilinx_tests/project1.vhd:111]

 

I have included the IEEE standard library and IEEE std_logic_1164  as follows:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

 

entity project1 is

 

port

(

clk         : in std_logic;
reset      : in std_logic;

signal_1 : out std_logic_vector

);

 

Synthesis exits after 20 of the [Synth 8-1031] errors with a final error:

ERROR: [Common 17-39] 'source' failed due to earlier errors.

 

Googling this error produces no useful results so I am hoping the Xilinx community can point out what might be producing the Synth 8-1031 errors.

 

This problem seems similar to hemanthkumar's reply to [Synth 8-4169] error in use clause].

 

Thank you.

 

 

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1 Solution

Accepted Solutions
Visitor willparker
Visitor
17,107 Views
Registered: ‎03-20-2014

Re: Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

Jump to solution

driesd,

 

Thank you for the quick response.

 

When I tried to create a representative project to replicate the error, I think I discovered the solution:

 

I used a package definition in my larger project, but I did not include the IEEE library and ieee.std_logic_1164.all again after the initial entity definition.

 

The code below works unless the highlighted library usage statement after the entity definition is removed.

 

-------------------------------------------------------------------------------

--Test Case for Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

--------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;  

 

entity project1 is

port (

clk        : in std_logic;

reset      : in std_logic;

pin_1 : in std_logic_vector (1 downto 0);

pin_2 : out std_logic_vector (1 downto 0) );

 

end project1;  

 

-------------------------------------------------------------

--problem area

--Restating these library usage statements fixes the synthesis error

 

library ieee;  

use ieee.std_logic_1164.all;

 

---------------------------------------------------------------------------

   

package project1_pkg is  

  component project1 is   

  port  (  

  clk        : in std_logic;

  reset      : in std_logic;  

   pin_1 : in std_logic_vector (1 downto 0);

  pin_2 : out std_logic_vector (1 downto 0)  

  );

  end component; end project1_pkg;

architecture rtl of project1 is

signal d_to_q : std_logic_vector(1 downto 0);

begin --rtl architecture

DFF : process(clk)

begin  

if rising_edge(clk) then

    if (reset = '1') then    d_to_q <= "00";

 else        d_to_q <= pin_1;

 end if; --reset  

end if; --rising edge of clk end process;

pin_2 <= d_to_q;

end architecture;

 

 

 

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2 Replies
Xilinx Employee
Xilinx Employee
11,472 Views
Registered: ‎11-28-2007

Re: Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

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Hi Will,

 

can you share your VHDL file or a testcase file so we can try to reproduce the issue?

 

At first, I don't see anything wrong with your code other than the fact that signal_1 is an unconstrained vector.

 

 

Best regards,

Dries

--------------------------------------------------------------------------------------------------------------------
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Visitor willparker
Visitor
17,108 Views
Registered: ‎03-20-2014

Re: Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

Jump to solution

driesd,

 

Thank you for the quick response.

 

When I tried to create a representative project to replicate the error, I think I discovered the solution:

 

I used a package definition in my larger project, but I did not include the IEEE library and ieee.std_logic_1164.all again after the initial entity definition.

 

The code below works unless the highlighted library usage statement after the entity definition is removed.

 

-------------------------------------------------------------------------------

--Test Case for Vivado 2013.4 ERROR: [Synth 8-1031] std_logic is not declared

--------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;  

 

entity project1 is

port (

clk        : in std_logic;

reset      : in std_logic;

pin_1 : in std_logic_vector (1 downto 0);

pin_2 : out std_logic_vector (1 downto 0) );

 

end project1;  

 

-------------------------------------------------------------

--problem area

--Restating these library usage statements fixes the synthesis error

 

library ieee;  

use ieee.std_logic_1164.all;

 

---------------------------------------------------------------------------

   

package project1_pkg is  

  component project1 is   

  port  (  

  clk        : in std_logic;

  reset      : in std_logic;  

   pin_1 : in std_logic_vector (1 downto 0);

  pin_2 : out std_logic_vector (1 downto 0)  

  );

  end component; end project1_pkg;

architecture rtl of project1 is

signal d_to_q : std_logic_vector(1 downto 0);

begin --rtl architecture

DFF : process(clk)

begin  

if rising_edge(clk) then

    if (reset = '1') then    d_to_q <= "00";

 else        d_to_q <= pin_1;

 end if; --reset  

end if; --rising edge of clk end process;

pin_2 <= d_to_q;

end architecture;

 

 

 

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