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Observer rschilling
Observer
13,775 Views
Registered: ‎10-14-2014

Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Hi guys,

 

I want to assign following variable:

 

v_bust_len_original(11-v_shift_burst_size downto 0) := v_data_read(11 downto v_shift_burst_size);

 

Unfortunately, this result in the error message:  [Synth 8-561] range expression could not be resolved to a constant

It seems that Vivado doesn't fully support this dynamic assignments.

However, how can I rewrite this clause to make it synthesizable? (v_shift_burst_size is an integer ranged from 0 to 7).

 

Best regards

Robert

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Scholar muravin
Scholar
24,603 Views
Registered: ‎11-21-2013

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Robert,

 

You need to write a case or an if-elsif chain against all possible permutations of v_shift_burst_size.

 

If my memory is correct, you only need to have a constant expression on the left side of the assignment, the right side may be left with a signal.


i.e.

case (v_shift_burst_size) is
  when others => v_bust_len_original(11-0 downto 0) := v_data_read(11 downto v_shift_burst_size);
  when 1 => v_bust_len_original(11-1 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 2 => v_bust_len_original(11-2 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 3 => v_bust_len_original(11-3 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 4 => v_bust_len_original(11-4 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 5 => v_bust_len_original(11-5 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 6 => v_bust_len_original(11-6 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 7 => v_bust_len_original(11-7 downto 0) := v_data_read(11 downto v_shift_burst_size);

end case;

 

Hope this helps.

Vlad

Vladislav Muravin
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Historian
Historian
13,757 Views
Registered: ‎02-25-2008

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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@rschilling wrote:

Hi guys,

 

I want to assign following variable:

 

v_bust_len_original(11-v_shift_burst_size downto 0) := v_data_read(11 downto v_shift_burst_size);

 

Unfortunately, this result in the error message:  [Synth 8-561] range expression could not be resolved to a constant

It seems that Vivado doesn't fully support this dynamic assignments.

However, how can I rewrite this clause to make it synthesizable? (v_shift_burst_size is an integer ranged from 0 to 7).

 


It's certainly legal VHDL but it can't be synthesized. The indices need to be constant at compile time.

 

You should be able to sort of unroll the whole thing and use a loop to do the assignment to the various bits based on the v_shift_burst_size variable.

----------------------------Yes, I do this for a living.
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Scholar muravin
Scholar
24,604 Views
Registered: ‎11-21-2013

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Robert,

 

You need to write a case or an if-elsif chain against all possible permutations of v_shift_burst_size.

 

If my memory is correct, you only need to have a constant expression on the left side of the assignment, the right side may be left with a signal.


i.e.

case (v_shift_burst_size) is
  when others => v_bust_len_original(11-0 downto 0) := v_data_read(11 downto v_shift_burst_size);
  when 1 => v_bust_len_original(11-1 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 2 => v_bust_len_original(11-2 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 3 => v_bust_len_original(11-3 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 4 => v_bust_len_original(11-4 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 5 => v_bust_len_original(11-5 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 6 => v_bust_len_original(11-6 downto 0) := v_data_read(11 downto v_shift_burst_size);

  when 7 => v_bust_len_original(11-7 downto 0) := v_data_read(11 downto v_shift_burst_size);

end case;

 

Hope this helps.

Vlad

Vladislav Muravin
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10,107 Views
Registered: ‎04-25-2016

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Hi,

stumble upon the smiliar issue with Vivado 2015.3 and 2016.1

 

here is my 'problematic' (from a Vivado of course) code snippet :

 

architecture RTL of DLY_VAR is

  signal reg     : std_logic_vector(2**K -1 downto 0);
  signal DLY_int : integer range 1 to 2**K-1;

begin  --  of arch

  main : process(NRST, CLK)
  begin
    if NRST = '1' then
      B       <= '0';
      reg     <= (others => '0');
      DLY_int <= 1;

    elsif rising_edge(CLK) then
      if EN = '1' then

        -- latching the queuing delay value
        DLY_int <= 2**to_integer(unsigned(DLY));

        if DLY_int = 1 then
          B <= A;
        else
          reg(0)                  <= A;  -- input to queue
          reg(DLY_int-1 downto 1) <= reg(DLY_int-2 downto 0);  --shifting
          B                       <= reg(DLY_int -1);          --output
        end if;

      end if;
    end if;
  end process main;

end architecture RTL;

This is a shame! since it gets fully synthetized with ISE 14.7 and Quartus 15 (Altera).

 

@Xilinx: Why such a regression?! WtF, are you sleeping or what?!^^
This is *not* the way for people switching to Vivado, better off sticking with ISE!

 

Florian

 

Scholar dpaul24
Scholar
8,445 Views
Registered: ‎08-07-2014

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Using Vivado 2015.4 and having the same problem! Created a new thread.

This is a shame! since it gets fully synthetized with ISE 14.7 and Quartus 15 (Altera).

:-o

Disappointed to hear this. But for 7 series devices, I must use Viv 2015.4!

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
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Explorer
Explorer
4,578 Views
Registered: ‎09-19-2010

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Vivado 2017.2 

The same issue here! 

Xilinx guys work very hard :D :D 

Visitor bsmann
Visitor
4,261 Views
Registered: ‎04-16-2013

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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@florianfrank14: I so fully agree, you should not adopt code, valid code, to a tool !

 

@ all Vivado creators: This is absolute bull$hit to say the very least !!!

 

We had a company internal package for re-usable design units. "Code" that has been used for years and years and years in various environments and for various FPGAs (Xilinx Virtex-2, Virtex-6, different CPLDs and FPGAs from Lattice and Actel) and hence with various tools (ISE since version 10, Various DesignExpert, various ispLever versions, Libero...) and also different simulators (Modelsim, various Active-HDL versions) ... it has all worked out perfectly fine

 

... until Vivado came along !!!

 

So the necessity to now duplicate the code and re-write it (because it is still used by old tools when re-compiling older projects and risking changing behavior there is not an option).

 

IP-centric workflow with design re-use is how it is euphemistically called in the Vivado marketing ... but duplication is what is necessary instead

 

IMHO a new tool version can incorporate many many things (from new GUI over new capabilities, performance improvements up to licensing price increments) but it should not render previously done and proven-good work useless !

 

Bjoern

Observer jsammy
Observer
3,095 Views
Registered: ‎09-19-2014

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Can confirm this is still broken in 2017.4.

I use the word "broken", even though this post is marked as solved specifically because of @bsmann's point regarding code reuse and the inability to use shared proven HDL in Vivado projects.

This needs to be a regression that is fixed going forward.
3,086 Views
Registered: ‎04-25-2016

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Thanks for checking in Vivado 2017.4 !

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Participant a.gamez
Participant
3,075 Views
Registered: ‎05-12-2016

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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This syntax was working fine on a ISE 14.4 project I have, that I cannot migrate to Vivado because of this. How come it did work a decade ago but it doesn't work on vivado?

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Visitor bsmann
Visitor
1,779 Views
Registered: ‎04-16-2013

Re: Vivado 2014.2: [Synth 8-561] range expression could not be resolved to a constant

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Hi @jsammy

 

yes it is still broken. So, as we were forced to move from ISE to Vivado using Artix (and to be fair, Vivado also has many plus sides as well as negative ones) we needed to duplicate sources and re-worked them.

 

In all our cases this could be done by using shift (SLL, SRL) functions with dynamic parameters instead of vectors with dynamic ranges.

 

So going from old version:

 

 

-- Helper function " U = Fi_Unsigned (V)" converts a std_logic_vector V to an unsigned integer U.
-- all inputs (p.ve_ and p.e_ ) are values set by software during run time (std_logic_vector or std_logic format)

si_Cmd_Length <= (Fi_Unsigned (p.ve_Cmd_Length) + 1) when (p.e_Cmd_LenZero = '0') else 0;

if (bLSB_nMSBfirst) then
    sv_SPI_Write <= p.v_WrData;
else
    sv_SPI_Write(sv_SPI_Write ' left downto sv_SPI_Write ' left - si_Cmd_Length + 1) <= p.v_WrData (si_Cmd_Length - 1 downto 0);
end if;

 

 

to new version

 

 

if (bLSB_nMSBfirst) then
sv_SPI_Write <= p.v_WrData;
else
sv_SPI_Write <= p.v_WrData SLL (32 - (si_Cmd_Length + Fi_Unsigned (p.ve_DataPulses) + 1));
end if;

Even if I have to admit that that the new version is quite a bit more readable (and should be technically equivalent and hence likely should work also in the old designs), I still think that the decision to update/change legit and proven code should be at the users discretion.

 

But maybe the above snippets might help you guys to adopt your existing RTL (if you decide to do so) or might even inspire the Vivado creators on how to silently translate this old RTL into something functional equivalent that Vivado Synthesis will compile ;-).

 

Björn

 

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