04-01-2015 11:33 PM
I am having issues synthesizing my modules with Vivado 2014.4 when I integrate a true dual port bram with write enable.
Basically, I get a Synthesis failed popup and when I look at my logs I only see the last lines as
INFO: [Synth 8-4652] Swapped enable and write-enable on 6 RAM instances of RAM bins_mem/ram_reg to conserve power
Optimized 10 bits of RAM "output_fifo/fifo_buffer_reg" due to constant propagation. Old ram width 32 bits, new ram width 22 bits
INFO: [Synth 8-3971] The signal min_max_config_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM min_max_config_reg to conserve power
I have my suspicion on the introduction of a byte enabled true dual port bram. I used the Vivado recommended template from UG 901 (version : Dec 2014) as below. When I remove this module in my design I am able to synthesize successfully. Is there a work around to be able to synthesize with the template. I also plan to use an asymmetric version later on but for now want to be sure this synthesizes.
// True-Dual-Port BRAM with Byte-wide Write Enable
// Write-First mode
// File: HDL_Coding_Techniques/rams/bytewrite_tdp_ram_wf.v
//
// ByteWide Write Enable, - WRITE_FIRST mode template - Vivado recomended
module bytewrite_tdp_ram_wf
#(
//----------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clka,
input ena,
input [NUM_COL-1:0] wea,
input [ADDR_WIDTH-1:0] addra,
input [DATA_WIDTH-1:0] dina,
output reg [DATA_WIDTH-1:0] douta,
input clkb,
input enb,
input [NUM_COL-1:0] web,
input [ADDR_WIDTH-1:0] addrb,
input [DATA_WIDTH-1:0] dinb,
output reg [DATA_WIDTH-1:0] doutb
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clka) begin
if(ena) begin
if(wea[i]) begin
ram_block[addra][i*COL_WIDTH +: COL_WIDTH] <= dina[i*COL_WIDTH +: COL_WIDTH];
douta[i*COL_WIDTH +: COL_WIDTH] <= dina[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
douta[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addra][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkb) begin
if(enb) begin
if(web[i]) begin
ram_block[addrb][i*COL_WIDTH +: COL_WIDTH] <= dinb[i*COL_WIDTH +: COL_WIDTH];
doutb[i*COL_WIDTH +: COL_WIDTH] <= dinb[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
doutb[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addrb][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
endmodule // v_bytewrite_tdp_ram_writefirst
03-14-2016 11:58 AM
Same behaviour in 2015.2, design is able to complete synthesis in 2015.4.
Thanks,
Anusheel
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04-01-2015 11:53 PM
04-02-2015 08:29 AM
I think the problem is with the write enable port.
When I synthesize this it finishes without any errors
module top(
clk,
addra,
dina ,
douta ,
addrb,
dinb,
doutb
);
input clk;
input [9:0] addra;
input [31:0] dina;
output [31:0] douta;
input [9:0] addrb;
input [31:0] dinb;
output [31:0] doutb;
bytewrite_tdp_ram_wf
#(
.NUM_COL ( 4 ),
.COL_WIDTH ( 8 ),
.ADDR_WIDTH ( 10 ), // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
.DATA_WIDTH ( 4*8 ) // Data Width in bits
//----------------------------------------------------------------------
)
page_table
(
// config port / control port
.clka (clk ),
.ena (1'b1 ),
.wea (4'b0001 ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
// output port
.clkb (clk ),
.enb (1'b1 ),
.web (4'b0001 ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
endmodule
But when I try this, I get a synthesis error with no warnings
module top(
clk,
addra,
dina ,
douta ,
addrb,
dinb,
doutb
);
input clk;
input [9:0] addra;
input [31:0] dina;
output [31:0] douta;
input [9:0] addrb;
input [31:0] dinb;
output [31:0] doutb;
bytewrite_tdp_ram_wf
#(
.NUM_COL ( 4 ),
.COL_WIDTH ( 8 ),
.ADDR_WIDTH ( 10 ), // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
.DATA_WIDTH ( 4*8 ) // Data Width in bits
//----------------------------------------------------------------------
)
page_table
(
// config port / control port
.clka (clk ),
.ena (1'b1 ),
.wea (4'b1110 ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
// output port
.clkb (clk ),
.enb (1'b1 ),
.web (4'b1100 ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
endmodule
Any idea
04-03-2015 08:02 AM
04-08-2015 06:25 AM
I am able to reproduce the issue with below message in the log file:
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
This issue is occurring with few values only. Currently I am working on this issue, I will post my findings.
Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
03-14-2016 10:32 AM
Has this problem been resolved in Vivado 2015.2?
03-14-2016 11:58 AM
Same behaviour in 2015.2, design is able to complete synthesis in 2015.4.
Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.
Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------