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Explorer
Explorer
10,230 Views
Registered: ‎07-03-2014

[Vivado 2015.1] FSM encoding report is not complete!

Hi!

 

I've been looking for an answer about the problem of Vivado not showing the FSM encoding in the synthesis report. It is supposed to have been solved in Vivado 2015.1 but I can't find it any anywy.

When synthesis is finished, you can check the state encoding of FSMs that have been re-encoded, but in each run not all of them are re-encoded. In fact, my design has 18 FSM and only 7 are showed in the report.

 

This makes ABSOLUTELY impossible to debug my design on hardware, since ILA doesn't show the state name in the waveform window, just the encoding of the state.

 

Is there any solution to this problem? I could manually encoded each state of each FSM, but that implies more than 300 states, which make it hard enough to discard.

 

Thanks!

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21 Replies
Xilinx Employee
Xilinx Employee
10,201 Views
Registered: ‎08-01-2008

Re: [Vivado 2015.1] FSM encoding report is not complete!

make sure if you enable right Swtich in in Sysnthsis property

Thanks and Regards
Balkrishan
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Explorer
Explorer
10,190 Views
Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Yes, I always select "auto" in "-fsm_extraction" option.

It looks like it is not olny me, but some other FPGA colleagues report the same problem.
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Xilinx Employee
Xilinx Employee
10,181 Views
Registered: ‎02-16-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Hi,

 

You can find the FSM encoding in .os file created.

 

In the synthesis log did you find any info messages indicating the FSM inference and FSM encoding for the remaining FSMs?

Can you cross-check if you can see the encoding in .os file?

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Explorer
Explorer
10,174 Views
Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

The .os file contains the same information that shows the Vivado synthesis report, just the FSM which are re-encoded, but not all. Besides, the state names are not showed, so it is impossible to be 100% sure which encoding matches with the state:

 

 add_fsm_encoding \
       {T2_Framer.estado_out} \
       { }  \
       {{000 000} {001 001} {010 010} {011 011} {100 100} {101 101} {110 110} {111 111} }

 

How do you know which state is each binary code??

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Xilinx Employee
Xilinx Employee
10,134 Views
Registered: ‎02-16-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Hi,

 

Can you check if the FSMs are being inferred by the tool or not for the other 11 FSMs in your design?

You can check it from the synthesis log info messages.

 

On these 11 FSMs can you try applying FSM_attribute in the RTL?

 

(* fsm_encoding = “auto” *) reg [7:0] my_state;

 

For more details on this attribute check pageno:43 in the below user guide.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug901-vivado-synthesis.pdf

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Moderator
Moderator
10,122 Views
Registered: ‎01-16-2013

Re: [Vivado 2015.1] FSM encoding report is not complete!

Hello @alexmoya,

 

The FSM encoding information will be displayed in synthesis log file. Please see FSM reporting section at page number 131 in following UG901:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug901-vivado-synthesis.pdf

 

Capture.PNG

 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
10,113 Views
Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Hi @syedz,

 

Which name is the synthsis log file? If it is [TOP].vds, in that file only appear the states of re-encoded FSM, not all the FSM in the design. The same occurs with "fsm_encoding.so", it shows only the re-encoded FSMs, not every FSM in the design.

 

UG901 doesn't explain this clearly, it says that FSM encoding appears in the log file, but that's not true. As I said in my first question, only the re-encoded FSM are shown:

 

---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
               wait_flag |                             0001 |                             0001
             decode_type |                             0010 |                             0010
             decode_app1 |                             0011 |                             0011
             decode_app2 |                             0100 |                             0100
             decode_app3 |                             0101 |                             0101
             decode_app4 |                             0110 |                             0110
                   valid |                             0111 |                             1001
            end_transfer |                             1000 |                             0111
                   error |                             1001 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_ctrl_reg' using encoding 'sequential' in module 'DMA_CTRL_Decoder'
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Explorer
Explorer
9,978 Views
Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Well, after some re-compilations and some re-design of my VHDL, I got this report which DOES include all FSMs in my design for the first time:

 

---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
               wait_flag |                             0001 |                             0001
             decode_type |                             0010 |                             0010
             decode_app1 |                             0011 |                             0011
             decode_app2 |                             0100 |                             0100
             decode_app3 |                             0101 |                             0101
             decode_app4 |                             0110 |                             0110
                   valid |                             0111 |                             1001
            end_transfer |                             1000 |                             0111
                   error |                             1001 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_ctrl_reg' using encoding 'sequential' in module 'DMA_CTRL_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                            00000 |                            00000
        wait_frame_start |                            00001 |                            00001
             get_fft_cfg |                            00010 |                            00010
              get_bw_cfg |                            00011 |                            00011
          get_bw_ext_cfg |                            00100 |                            00100
  get_guard_interval_cfg |                            00101 |                            00101
            get_miso_cfg |                            00110 |                            00110
             get_ppx_cfg |                            00111 |                            00111
            get_papr_cfg |                            01000 |                            01000
            get_fill_cfg |                            01001 |                            01001
           get_nf2_cfg_0 |                            01010 |                            01010
           get_nf2_cfg_1 |                            01011 |                            01011
                   valid |                            01100 |                            10001
         wait_ifft_ready |                            01101 |                            01100
      send_config_to_fft |                            01110 |                            01101
    config_loaded_to_fft |                            01111 |                            01110
            end_transfer |                            10000 |                            01111
                   error |                            10001 |                            10000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Frame_Config_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
    wait_for_l1_transfer |                             0001 |                             0001
           read_l1_pre_0 |                             0010 |                             0010
           read_l1_pre_1 |                             0011 |                             0011
           read_l1_pre_2 |                             0100 |                             0100
    wait_read_l1_pre_out |                             0101 |                             0101
   wait_read_l1_post_out |                             0110 |                             0111
            read_l1_post |                             0111 |                             0110
          unload_l1_post |                             1000 |                             1000
             insert_bias |                             1001 |                             1001
       check_dummy_cells |                             1010 |                             1010
            insert_dummy |                             1011 |                             1011
        end_dma_transfer |                             1100 |                             1100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'L1_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
   wait_for_plp_transfer |                              001 |                              001
         fill_pipeline_0 |                              010 |                              010
         fill_pipeline_1 |                              011 |                              011
         fill_pipeline_2 |                              100 |                              100
           read_plp_data |                              101 |                              101
         unload_pipeline |                              110 |                              110
        end_dma_transfer |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Data_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Dummy_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Unmod_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
         wait_new_symbol |                             0000 |                             0000
            check_symbol |                             0001 |                             0001
       wait_dma_permuted |                             0010 |                             0010
          write_permuted |                             0011 |                             0011
       start_read_lineal |                             0100 |                             0100
             read_lineal |                             0101 |                             0101
         wait_dma_lineal |                             0110 |                             0110
            write_lineal |                             0111 |                             0111
     start_read_permuted |                             1000 |                             1000
           read_permuted |                             1001 |                             1001
           finish_symbol |                             1010 |                             1010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Freq_Interleaver'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
         wait_new_symbol |                            00000 |                            00000
      wait_next_datacell |                            00001 |                            00001
     miso_get_datacell_0 |                            00010 |                            00010
    miso_wait_datacell_0 |                            00011 |                            00011
     miso_get_datacell_1 |                            00100 |                            00101
    miso_wait_datacell_1 |                            00101 |                            00110
miso_last_send_datacell_0 |                            00110 |                            01100
miso_last_next_datacell_0 |                            00111 |                            01101
miso_last_send_datacell_1 |                            01000 |                            01110
    miso_send_datacell_0 |                            01001 |                            00111
miso_wait_next_datacell_1 |                            01010 |                            01000
    miso_send_datacell_1 |                            01011 |                            01001
         miso_wait_state |                            01100 |                            01010
miso_wait_next_datacell_0 |                            01101 |                            01011
              miso_error |                            01110 |                            00100
     siso_get_datacell_0 |                            01111 |                            01111
    siso_wait_datacell_0 |                            10000 |                            10000
    siso_send_datacell_0 |                            10001 |                            10001
         siso_wait_state |                            10010 |                            10010
siso_wait_last_datacell_0 |                            10011 |                            10100
    siso_wait_datacell_1 |                            10100 |                            10011
 siso_last_send_datacell |                            10101 |                            10101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'MISO_Processor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
        wait_p1_transfer |                             0001 |                             0001
       wait_dma_complete |                             0010 |                             0010
            dma_complete |                             0011 |                             0011
           wait_p1_write |                             0100 |                             0100
  send_config_to_ifft_s0 |                             0101 |                             0101
config_loaded_to_ifft_s0 |                             0110 |                             0110
      write_p1_normal_s0 |                             0111 |                             0111
       write_p1_shift_s0 |                             1000 |                             1000
  send_config_to_ifft_s1 |                             1001 |                             1001
config_loaded_to_ifft_s1 |                             1010 |                             1010
      write_p1_normal_s1 |                             1011 |                             1011
       write_p1_shift_s1 |                             1100 |                             1100
               write_end |                             1101 |                             1101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_WR_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
            wait_p1_read |                             0001 |                             0001
             read_slot_0 |                             0010 |                             0010
             read_slot_1 |                             0011 |                             0011
          read_start_p1c |                             0100 |                             0100
          read_first_p1c |                             0101 |                             0101
                read_p1c |                             0110 |                             0110
          read_start_p1a |                             0111 |                             0111
          read_first_p1a |                             1000 |                             1000
                read_p1a |                             1001 |                             1001
          read_start_p1b |                             1010 |                             1010
          read_first_p1b |                             1011 |                             1011
                read_p1b |                             1100 |                             1100
           read_last_p1b |                             1101 |                             1101
                read_end |                             1110 |                             1110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_RD_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                          0000000 |                          0000000
     wait_for_new_symbol |                          0000001 |                          0000001
        p1_encode_symbol |                          0000010 |                          1000000
        p1_encode_t2base |                          0000011 |                          1000001
        p1_encode_t2lite |                          0000100 |                          1000010
        p1_encode_non_t2 |                          0000101 |                          1000011
           p1_set_slot_0 |                          0000110 |                          1000100
           p1_set_slot_1 |                          0000111 |                          1000101
   p1_wait_for_ifft_conf |                          0001000 |                          1000111
      p1_fill_first_ifft |                          0001001 |                          1001000
   p1_reset_carrier_ifft |                          0001010 |                          1001001
p1_read_rom_carrier_ifft |                          0001011 |                          1001010
    p1_fill_carrier_ifft |                          0001100 |                          1001011
       p1_fill_last_ifft |                          0001101 |                          1001100
       p1_wait_last_ifft |                          0001110 |                          1001101
  p1_encode_symbol_shift |                          0001111 |                          1001110
     p1_fill_first_shift |                          0010000 |                          1001111
  p1_reset_carrier_shift |                          0010001 |                          1010000
p1_read_rom_carrier_shift |                          0010010 |                          1010001
   p1_fill_carrier_shift |                          0010011 |                          1010010
      p1_fill_last_shift |                          0010100 |                          1010011
      p1_wait_last_shift |                          0010101 |                          1010100
          p1_wait_encode |                          0010110 |                          1000110
         p1_start_t2base |                          0010111 |                          1010101
         p1_start_t2lite |                          0011000 |                          1010110
         p1_start_non_t2 |                          0011001 |                          1010111
         p1_start_slot_0 |                          0011010 |                          1011000
         p1_start_slot_1 |                          0011011 |                          1011001
         p2_start_symbol |                          0011100 |                          0000011
     p2_wait_interleaver |                          0011101 |                          0000100
            p2_wait_ifft |                          0011110 |                          0000101
      p2_fill_first_ifft |                          0011111 |                          0000110
 p2_fill_get_first_extra |                          0100000 |                          0000111
     p2_fill_first_extra |                          0100001 |                          0001000
     p2_wait_first_extra |                          0100010 |                          0001001
        p2_fill_pipeline |                          0100011 |                          0001010
    p2_get_extra_pilot_0 |                          0100100 |                          0010110
 p2_insert_extra_pilot_0 |                          0100101 |                          0010111
    p2_get_extra_pilot_1 |                          0100110 |                          0011000
 p2_insert_extra_pilot_1 |                          0100111 |                          0011001
       p2_decide_carrier |                          0101000 |                          0001011
  p2_fill_get_last_extra |                          0101001 |                          0010001
      p2_fill_last_extra |                          0101010 |                          0010010
      p2_wait_last_extra |                          0101011 |                          0010011
       p2_fill_last_ifft |                          0101100 |                          0010100
       p2_wait_last_ifft |                          0101101 |                          0010101
            p2_insert_tr |                          0101110 |                          0001101
               p2_get_tr |                          0101111 |                          0001100
    p2_get_extra_pilot_2 |                          0110000 |                          0011010
 p2_insert_extra_pilot_2 |                          0110001 |                          0011011
    p2_get_extra_pilot_3 |                          0110010 |                          0011100
 p2_insert_extra_pilot_3 |                          0110011 |                          0011101
            p2_get_pilot |                          0110100 |                          0001110
         p2_insert_pilot |                          0110101 |                          0001111
      p2_insert_datacell |                          0110110 |                          0010000
       data_start_symbol |                          0110111 |                          0011110
   data_wait_interleaver |                          0111000 |                          0011111
          data_wait_ifft |                          0111001 |                          0100000
    data_fill_first_ifft |                          0111010 |                          0100001
      data_fill_pipeline |                          0111011 |                          0100010
  data_insert_first_edge |                          0111100 |                          0100011
     data_decide_carrier |                          0111101 |                          0100100
      data_get_last_edge |                          0111110 |                          0101100
   data_insert_last_edge |                          0111111 |                          0101101
     data_fill_last_ifft |                          1000000 |                          0101110
     data_wait_last_ifft |                          1000001 |                          0101111
          data_insert_tr |                          1000010 |                          0101010
             data_get_tr |                          1000011 |                          0101011
data_get_continual_scattered |                          1000100 |                          0100111
      data_get_continual |                          1000101 |                          0100101
      data_get_scattered |                          1000110 |                          0100110
       data_insert_pilot |                          1000111 |                          0101000
    data_insert_datacell |                          1001000 |                          0101001
         fc_start_symbol |                          1001001 |                          0110000
     fc_wait_interleaver |                          1001010 |                          0110001
            fc_wait_ifft |                          1001011 |                          0110010
      fc_fill_first_ifft |                          1001100 |                          0110011
        fc_fill_pipeline |                          1001101 |                          0110100
    fc_insert_first_edge |                          1001110 |                          0110101
       fc_decide_carrier |                          1001111 |                          0110110
            fc_get_pilot |                          1010000 |                          0110111
         fc_insert_pilot |                          1010001 |                          0111000
        fc_get_last_edge |                          1010010 |                          0111100
     fc_insert_last_edge |                          1010011 |                          0111101
       fc_fill_last_ifft |                          1010100 |                          0111110
       fc_wait_last_ifft |                          1010101 |                          0111111
        finish_ifft_load |                          1010110 |                          0000010
            fc_insert_tr |                          1010111 |                          0111010
               fc_get_tr |                          1011000 |                          0111011
      fc_insert_datacell |                          1011001 |                          0111001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Symbol_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
    wait_p1_start_encode |                              001 |                              001
      wait_p1_end_encode |                              010 |                              010
         wait_ifft_ready |                              011 |                              011
             start_frame |                              100 |                              100
        insert_p1_symbol |                              101 |                              101
         wait_symbol_end |                              110 |                              110
              symbol_end |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_out_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                            00000
         wait_s1_s2_data |                             0001 |                            00001
            wait_ifft_p1 |                             0010 |                            00010
        encode_p1_symbol |                             0011 |                            00011
        wait_p1_encoding |                             0100 |                            00100
               end_frame |                             0101 |                            00101
        wait_frame_start |                             0110 |                            00110
    get_frame_parameters |                             0111 |                            00111
           new_p1_t2base |                             1000 |                            01000
      assemble_p1_symbol |                             1001 |                            01001
           new_p2_symbol |                             1010 |                            01010
      assemble_p2_symbol |                             1011 |                            01011
         new_data_symbol |                             1100 |                            01100
    assemble_data_symbol |                             1101 |                            01101
           new_fc_symbol |                             1110 |                            01110
      assemble_fc_symbol |                             1111 |                            01111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
                    idle |                             0001 |                             0001
            process_conf |                             0010 |                             0010
              process_l1 |                             0011 |                             0011
             process_plp |                             0100 |                             0100
           process_dummy |                             0101 |                             0101
             process_aux |                             0110 |                             0110
           process_unmod |                             0111 |                             0111
             process_fef |                             1000 |                             1000
              process_p1 |                             1001 |                             1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_DMA_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 654.523 ; gain = 476.461
---------------------------------------------------------------------------------

I'll post the report next time I synthesize the design and some of the FSMs disappear.

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9,954 Views
Registered: ‎05-27-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

When you said "recoding", what exactly did that entail?  I have transferred a design from ISE 2014.7 to Vivado 2015.1 and it is kicking my behind with timing issues until I noticed the FSMs are not being inferred.

 

Any help would be appreciated.

 

I was using a basic FSM based on the built-in templates in ISE, but they are not working now.

 

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Explorer
Explorer
9,230 Views
Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Well, after 7 re-synthesis, now one of the FSMs has disappeared:

 

---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
               wait_flag |                             0001 |                             0001
             decode_type |                             0010 |                             0010
             decode_app1 |                             0011 |                             0011
             decode_app2 |                             0100 |                             0100
             decode_app3 |                             0101 |                             0101
             decode_app4 |                             0110 |                             0110
                   valid |                             0111 |                             1001
            end_transfer |                             1000 |                             0111
                   error |                             1001 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_ctrl_reg' using encoding 'sequential' in module 'DMA_CTRL_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                            00000 |                            00000
        wait_frame_start |                            00001 |                            00001
             get_fft_cfg |                            00010 |                            00010
              get_bw_cfg |                            00011 |                            00011
          get_bw_ext_cfg |                            00100 |                            00100
  get_guard_interval_cfg |                            00101 |                            00101
            get_miso_cfg |                            00110 |                            00110
             get_ppx_cfg |                            00111 |                            00111
            get_papr_cfg |                            01000 |                            01000
            get_fill_cfg |                            01001 |                            01001
           get_nf2_cfg_0 |                            01010 |                            01010
           get_nf2_cfg_1 |                            01011 |                            01011
                   valid |                            01100 |                            10001
         wait_ifft_ready |                            01101 |                            01100
      send_config_to_fft |                            01110 |                            01101
    config_loaded_to_fft |                            01111 |                            01110
            end_transfer |                            10000 |                            01111
                   error |                            10001 |                            10000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Frame_Config_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
    wait_for_l1_transfer |                             0001 |                             0001
           read_l1_pre_0 |                             0010 |                             0010
           read_l1_pre_1 |                             0011 |                             0011
           read_l1_pre_2 |                             0100 |                             0100
    wait_read_l1_pre_out |                             0101 |                             0101
   wait_read_l1_post_out |                             0110 |                             0111
            read_l1_post |                             0111 |                             0110
          unload_l1_post |                             1000 |                             1000
             insert_bias |                             1001 |                             1001
       check_dummy_cells |                             1010 |                             1010
            insert_dummy |                             1011 |                             1011
        end_dma_transfer |                             1100 |                             1100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'L1_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
   wait_for_plp_transfer |                              001 |                              001
         fill_pipeline_0 |                              010 |                              010
         fill_pipeline_1 |                              011 |                              011
         fill_pipeline_2 |                              100 |                              100
           read_plp_data |                              101 |                              101
         unload_pipeline |                              110 |                              110
        end_dma_transfer |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Data_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Dummy_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Unmod_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
         wait_new_symbol |                            00000 |                            00000
      wait_next_datacell |                            00001 |                            00001
     miso_get_datacell_0 |                            00010 |                            00010
    miso_wait_datacell_0 |                            00011 |                            00011
     miso_get_datacell_1 |                            00100 |                            00101
    miso_wait_datacell_1 |                            00101 |                            00110
miso_last_send_datacell_0 |                            00110 |                            01100
miso_last_next_datacell_0 |                            00111 |                            01101
miso_last_send_datacell_1 |                            01000 |                            01110
    miso_send_datacell_0 |                            01001 |                            00111
miso_wait_next_datacell_1 |                            01010 |                            01000
    miso_send_datacell_1 |                            01011 |                            01001
         miso_wait_state |                            01100 |                            01010
miso_wait_next_datacell_0 |                            01101 |                            01011
              miso_error |                            01110 |                            00100
     siso_get_datacell_0 |                            01111 |                            01111
    siso_wait_datacell_0 |                            10000 |                            10000
    siso_send_datacell_0 |                            10001 |                            10001
         siso_wait_state |                            10010 |                            10010
siso_wait_last_datacell_0 |                            10011 |                            10100
    siso_wait_datacell_1 |                            10100 |                            10011
 siso_last_send_datacell |                            10101 |                            10101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'MISO_Processor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
        wait_p1_transfer |                             0001 |                             0001
       wait_dma_complete |                             0010 |                             0010
            dma_complete |                             0011 |                             0011
           wait_p1_write |                             0100 |                             0100
  send_config_to_ifft_s0 |                             0101 |                             0101
config_loaded_to_ifft_s0 |                             0110 |                             0110
      write_p1_normal_s0 |                             0111 |                             0111
       write_p1_shift_s0 |                             1000 |                             1000
  send_config_to_ifft_s1 |                             1001 |                             1001
config_loaded_to_ifft_s1 |                             1010 |                             1010
      write_p1_normal_s1 |                             1011 |                             1011
       write_p1_shift_s1 |                             1100 |                             1100
               write_end |                             1101 |                             1101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_WR_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
            wait_p1_read |                             0001 |                             0001
             read_slot_0 |                             0010 |                             0010
             read_slot_1 |                             0011 |                             0011
          read_start_p1c |                             0100 |                             0100
          read_first_p1c |                             0101 |                             0101
                read_p1c |                             0110 |                             0110
          read_start_p1a |                             0111 |                             0111
          read_first_p1a |                             1000 |                             1000
                read_p1a |                             1001 |                             1001
          read_start_p1b |                             1010 |                             1010
          read_first_p1b |                             1011 |                             1011
                read_p1b |                             1100 |                             1100
           read_last_p1b |                             1101 |                             1101
                read_end |                             1110 |                             1110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_RD_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                          0000000 |                          0000000
     wait_for_new_symbol |                          0000001 |                          0000001
        p1_encode_symbol |                          0000010 |                          1000000
        p1_encode_t2base |                          0000011 |                          1000001
        p1_encode_t2lite |                          0000100 |                          1000010
        p1_encode_non_t2 |                          0000101 |                          1000011
           p1_set_slot_0 |                          0000110 |                          1000100
           p1_set_slot_1 |                          0000111 |                          1000101
   p1_wait_for_ifft_conf |                          0001000 |                          1000111
      p1_fill_first_ifft |                          0001001 |                          1001000
   p1_reset_carrier_ifft |                          0001010 |                          1001001
p1_read_rom_carrier_ifft |                          0001011 |                          1001010
    p1_fill_carrier_ifft |                          0001100 |                          1001011
       p1_fill_last_ifft |                          0001101 |                          1001100
       p1_wait_last_ifft |                          0001110 |                          1001101
  p1_encode_symbol_shift |                          0001111 |                          1001110
     p1_fill_first_shift |                          0010000 |                          1001111
  p1_reset_carrier_shift |                          0010001 |                          1010000
p1_read_rom_carrier_shift |                          0010010 |                          1010001
   p1_fill_carrier_shift |                          0010011 |                          1010010
      p1_fill_last_shift |                          0010100 |                          1010011
      p1_wait_last_shift |                          0010101 |                          1010100
          p1_wait_encode |                          0010110 |                          1000110
         p1_start_t2base |                          0010111 |                          1010101
         p1_start_t2lite |                          0011000 |                          1010110
         p1_start_non_t2 |                          0011001 |                          1010111
         p1_start_slot_0 |                          0011010 |                          1011000
         p1_start_slot_1 |                          0011011 |                          1011001
         p2_start_symbol |                          0011100 |                          0000011
     p2_wait_interleaver |                          0011101 |                          0000100
            p2_wait_ifft |                          0011110 |                          0000101
      p2_fill_first_ifft |                          0011111 |                          0000110
 p2_fill_get_first_extra |                          0100000 |                          0000111
     p2_fill_first_extra |                          0100001 |                          0001000
     p2_wait_first_extra |                          0100010 |                          0001001
        p2_fill_pipeline |                          0100011 |                          0001010
    p2_get_extra_pilot_0 |                          0100100 |                          0010110
 p2_insert_extra_pilot_0 |                          0100101 |                          0010111
    p2_get_extra_pilot_1 |                          0100110 |                          0011000
 p2_insert_extra_pilot_1 |                          0100111 |                          0011001
       p2_decide_carrier |                          0101000 |                          0001011
  p2_fill_get_last_extra |                          0101001 |                          0010001
      p2_fill_last_extra |                          0101010 |                          0010010
      p2_wait_last_extra |                          0101011 |                          0010011
       p2_fill_last_ifft |                          0101100 |                          0010100
       p2_wait_last_ifft |                          0101101 |                          0010101
            p2_insert_tr |                          0101110 |                          0001101
               p2_get_tr |                          0101111 |                          0001100
    p2_get_extra_pilot_2 |                          0110000 |                          0011010
 p2_insert_extra_pilot_2 |                          0110001 |                          0011011
    p2_get_extra_pilot_3 |                          0110010 |                          0011100
 p2_insert_extra_pilot_3 |                          0110011 |                          0011101
            p2_get_pilot |                          0110100 |                          0001110
         p2_insert_pilot |                          0110101 |                          0001111
      p2_insert_datacell |                          0110110 |                          0010000
       data_start_symbol |                          0110111 |                          0011110
   data_wait_interleaver |                          0111000 |                          0011111
          data_wait_ifft |                          0111001 |                          0100000
    data_fill_first_ifft |                          0111010 |                          0100001
      data_fill_pipeline |                          0111011 |                          0100010
  data_insert_first_edge |                          0111100 |                          0100011
     data_decide_carrier |                          0111101 |                          0100100
      data_get_last_edge |                          0111110 |                          0101100
   data_insert_last_edge |                          0111111 |                          0101101
     data_fill_last_ifft |                          1000000 |                          0101110
     data_wait_last_ifft |                          1000001 |                          0101111
          data_insert_tr |                          1000010 |                          0101010
             data_get_tr |                          1000011 |                          0101011
data_get_continual_scattered |                          1000100 |                          0100111
      data_get_continual |                          1000101 |                          0100101
      data_get_scattered |                          1000110 |                          0100110
       data_insert_pilot |                          1000111 |                          0101000
    data_insert_datacell |                          1001000 |                          0101001
         fc_start_symbol |                          1001001 |                          0110000
     fc_wait_interleaver |                          1001010 |                          0110001
            fc_wait_ifft |                          1001011 |                          0110010
      fc_fill_first_ifft |                          1001100 |                          0110011
        fc_fill_pipeline |                          1001101 |                          0110100
    fc_insert_first_edge |                          1001110 |                          0110101
       fc_decide_carrier |                          1001111 |                          0110110
            fc_get_pilot |                          1010000 |                          0110111
         fc_insert_pilot |                          1010001 |                          0111000
        fc_get_last_edge |                          1010010 |                          0111100
     fc_insert_last_edge |                          1010011 |                          0111101
       fc_fill_last_ifft |                          1010100 |                          0111110
       fc_wait_last_ifft |                          1010101 |                          0111111
        finish_ifft_load |                          1010110 |                          0000010
            fc_insert_tr |                          1010111 |                          0111010
               fc_get_tr |                          1011000 |                          0111011
      fc_insert_datacell |                          1011001 |                          0111001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Symbol_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
    wait_p1_start_encode |                              001 |                              001
      wait_p1_end_encode |                              010 |                              010
         wait_ifft_ready |                              011 |                              011
             start_frame |                              100 |                              100
        insert_p1_symbol |                              101 |                              101
         wait_symbol_end |                              110 |                              110
              symbol_end |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_out_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                            00000
         wait_s1_s2_data |                             0001 |                            00001
            wait_ifft_p1 |                             0010 |                            00010
        encode_p1_symbol |                             0011 |                            00011
        wait_p1_encoding |                             0100 |                            00100
               end_frame |                             0101 |                            00101
        wait_frame_start |                             0110 |                            00110
    get_frame_parameters |                             0111 |                            00111
           new_p1_t2base |                             1000 |                            01000
      assemble_p1_symbol |                             1001 |                            01001
           new_p2_symbol |                             1010 |                            01010
      assemble_p2_symbol |                             1011 |                            01011
         new_data_symbol |                             1100 |                            01100
    assemble_data_symbol |                             1101 |                            01101
           new_fc_symbol |                             1110 |                            01110
      assemble_fc_symbol |                             1111 |                            01111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
                    idle |                             0001 |                             0001
            process_conf |                             0010 |                             0010
              process_l1 |                             0011 |                             0011
             process_plp |                             0100 |                             0100
           process_dummy |                             0101 |                             0101
             process_aux |                             0110 |                             0110
           process_unmod |                             0111 |                             0111
             process_fef |                             1000 |                             1000
              process_p1 |                             1001 |                             1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_DMA_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------

You can compare with the report I posted above and you can check that "Freq_Interleaver" state machine has completely disappeared.

 

Why? What's happening? I've wasted more than 2 weeks with this and here in my company we are really exasperated with Vivado... We can't achieve any progress since we can't debug on hardware.

 

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Explorer
Explorer
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Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

Kind of the same is happening to me. I'm migrating a project that was succesfully implemented on Virtex 4 and ISE 10.1, and the hardware has been sold with success.
Now, I'm porting all the VHDL code to Vivado 2015.1 and NOTHING works: FSMs are sometimes inferred, sometimes not, muxes created with "with XXX select" are not implemented, some registers are added misteriously by the implementation step, processes which select between signals are simplified and don't work properly.....
Shameful!!
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Registered: ‎07-21-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

@alexmoya

 

As I can understand from your last post, ISE was able to infer correct FSM logic.

Please share the complete project with testbench for us to debug this issue further. Do you have access to open SR?

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

I must ask for permission to my boss before I can share my work.

 

I guess SR means "Software Repository", doesn't it? We are using our own private repository for version control.

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Registered: ‎07-21-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

@alexmoya

 

Let me know if you can share the project, I will send you an EZmove link to upload the archive of project.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Registered: ‎07-03-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

@anusheel

 

Sorry to say that I can't upload the source code to any repository due to tight confidentiality policy.

 

Anyway, it seems this bug has been solved in 2015.2, because so far, all compilation have reported all FSMs succesfully.

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Re: [Vivado 2015.1] FSM encoding report is not complete!

@alexmoya

 

Thanks for the update. Please close the thread.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Re: [Vivado 2015.1] FSM encoding report is not complete!

@anusheel

 

Well, it looks like it is not solved in Vivado 2015.2. Just a seconds ago, another FSM has disappeared suddenly from the report:

 

---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
               wait_flag |                             0001 |                             0001
             decode_type |                             0010 |                             0010
             decode_app1 |                             0011 |                             0011
             decode_app2 |                             0100 |                             0100
             decode_app3 |                             0101 |                             0101
             decode_app4 |                             0110 |                             0110
                   valid |                             0111 |                             1001
            end_transfer |                             1000 |                             0111
                   error |                             1001 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_ctrl_reg' using encoding 'sequential' in module 'DMA_CTRL_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                            00000 |                            00000
        wait_frame_start |                            00001 |                            00001
             get_fft_cfg |                            00010 |                            00010
              get_bw_cfg |                            00011 |                            00011
          get_bw_ext_cfg |                            00100 |                            00100
  get_guard_interval_cfg |                            00101 |                            00101
            get_miso_cfg |                            00110 |                            00110
             get_ppx_cfg |                            00111 |                            00111
            get_papr_cfg |                            01000 |                            01000
            get_fill_cfg |                            01001 |                            01001
           get_nf2_cfg_0 |                            01010 |                            01010
           get_nf2_cfg_1 |                            01011 |                            01011
                   valid |                            01100 |                            10001
         wait_ifft_ready |                            01101 |                            01100
      send_config_to_fft |                            01110 |                            01101
    config_loaded_to_fft |                            01111 |                            01110
            end_transfer |                            10000 |                            01111
                   error |                            10001 |                            10000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Frame_Config_Decoder'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
   wait_for_plp_transfer |                              001 |                              001
         fill_pipeline_0 |                              010 |                              010
         fill_pipeline_1 |                              011 |                              011
         fill_pipeline_2 |                              100 |                              100
           read_plp_data |                              101 |                              101
         unload_pipeline |                              110 |                              110
        end_dma_transfer |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Data_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Dummy_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
 wait_for_dummy_transfer |                              001 |                              001
      end_dummy_transfer |                              010 |                              010
       write_dummy_cells |                              011 |                              011
        end_dma_transfer |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Unmod_Preprocessor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
         wait_new_symbol |                             0000 |                             0000
            check_symbol |                             0001 |                             0001
       wait_dma_permuted |                             0010 |                             0010
          write_permuted |                             0011 |                             0011
       start_read_lineal |                             0100 |                             0100
             read_lineal |                             0101 |                             0101
         wait_dma_lineal |                             0110 |                             0110
            write_lineal |                             0111 |                             0111
     start_read_permuted |                             1000 |                             1000
           read_permuted |                             1001 |                             1001
           finish_symbol |                             1010 |                             1010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Freq_Interleaver'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
         wait_new_symbol |                            00000 |                            00000
      wait_next_datacell |                            00001 |                            00001
     miso_get_datacell_0 |                            00010 |                            00010
    miso_wait_datacell_0 |                            00011 |                            00011
     miso_get_datacell_1 |                            00100 |                            00101
    miso_wait_datacell_1 |                            00101 |                            00110
miso_last_send_datacell_0 |                            00110 |                            01100
miso_last_next_datacell_0 |                            00111 |                            01101
miso_last_send_datacell_1 |                            01000 |                            01110
    miso_send_datacell_0 |                            01001 |                            00111
miso_wait_next_datacell_1 |                            01010 |                            01000
    miso_send_datacell_1 |                            01011 |                            01001
         miso_wait_state |                            01100 |                            01010
miso_wait_next_datacell_0 |                            01101 |                            01011
              miso_error |                            01110 |                            00100
     siso_get_datacell_0 |                            01111 |                            01111
    siso_wait_datacell_0 |                            10000 |                            10000
    siso_send_datacell_0 |                            10001 |                            10001
         siso_wait_state |                            10010 |                            10010
siso_wait_last_datacell_0 |                            10011 |                            10100
    siso_wait_datacell_1 |                            10100 |                            10011
 siso_last_send_datacell |                            10101 |                            10101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'MISO_Processor'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
        wait_p1_transfer |                             0001 |                             0001
       wait_dma_complete |                             0010 |                             0010
            dma_complete |                             0011 |                             0011
           wait_p1_write |                             0100 |                             0100
  send_config_to_ifft_s0 |                             0101 |                             0101
config_loaded_to_ifft_s0 |                             0110 |                             0110
      write_p1_normal_s0 |                             0111 |                             0111
       write_p1_shift_s0 |                             1000 |                             1000
  send_config_to_ifft_s1 |                             1001 |                             1001
config_loaded_to_ifft_s1 |                             1010 |                             1010
      write_p1_normal_s1 |                             1011 |                             1011
       write_p1_shift_s1 |                             1100 |                             1100
               write_end |                             1101 |                             1101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_WR_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
            wait_p1_read |                             0001 |                             0001
             read_slot_0 |                             0010 |                             0010
             read_slot_1 |                             0011 |                             0011
          read_start_p1c |                             0100 |                             0100
          read_first_p1c |                             0101 |                             0101
                read_p1c |                             0110 |                             0110
          read_start_p1a |                             0111 |                             0111
          read_first_p1a |                             1000 |                             1000
                read_p1a |                             1001 |                             1001
          read_start_p1b |                             1010 |                             1010
          read_first_p1b |                             1011 |                             1011
                read_p1b |                             1100 |                             1100
           read_last_p1b |                             1101 |                             1101
                read_end |                             1110 |                             1110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_RD_reg' using encoding 'sequential' in module 'P1_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                          0000000 |                          0000000
     wait_for_new_symbol |                          0000001 |                          0000001
        p1_encode_symbol |                          0000010 |                          1000000
        p1_encode_t2base |                          0000011 |                          1000001
        p1_encode_t2lite |                          0000100 |                          1000010
        p1_encode_non_t2 |                          0000101 |                          1000011
           p1_set_slot_0 |                          0000110 |                          1000100
           p1_set_slot_1 |                          0000111 |                          1000101
   p1_wait_for_ifft_conf |                          0001000 |                          1000111
      p1_fill_first_ifft |                          0001001 |                          1001000
   p1_reset_carrier_ifft |                          0001010 |                          1001001
p1_read_rom_carrier_ifft |                          0001011 |                          1001010
    p1_fill_carrier_ifft |                          0001100 |                          1001011
       p1_fill_last_ifft |                          0001101 |                          1001100
       p1_wait_last_ifft |                          0001110 |                          1001101
  p1_encode_symbol_shift |                          0001111 |                          1001110
     p1_fill_first_shift |                          0010000 |                          1001111
  p1_reset_carrier_shift |                          0010001 |                          1010000
p1_read_rom_carrier_shift |                          0010010 |                          1010001
   p1_fill_carrier_shift |                          0010011 |                          1010010
      p1_fill_last_shift |                          0010100 |                          1010011
      p1_wait_last_shift |                          0010101 |                          1010100
          p1_wait_encode |                          0010110 |                          1000110
         p1_start_t2base |                          0010111 |                          1010101
         p1_start_t2lite |                          0011000 |                          1010110
         p1_start_non_t2 |                          0011001 |                          1010111
         p1_start_slot_0 |                          0011010 |                          1011000
         p1_start_slot_1 |                          0011011 |                          1011001
         p2_start_symbol |                          0011100 |                          0000011
     p2_wait_interleaver |                          0011101 |                          0000100
            p2_wait_ifft |                          0011110 |                          0000101
      p2_fill_first_ifft |                          0011111 |                          0000110
 p2_fill_get_first_extra |                          0100000 |                          0000111
     p2_fill_first_extra |                          0100001 |                          0001000
     p2_wait_first_extra |                          0100010 |                          0001001
        p2_fill_pipeline |                          0100011 |                          0001010
    p2_get_extra_pilot_0 |                          0100100 |                          0010110
 p2_insert_extra_pilot_0 |                          0100101 |                          0010111
    p2_get_extra_pilot_1 |                          0100110 |                          0011000
 p2_insert_extra_pilot_1 |                          0100111 |                          0011001
       p2_decide_carrier |                          0101000 |                          0001011
  p2_fill_get_last_extra |                          0101001 |                          0010001
      p2_fill_last_extra |                          0101010 |                          0010010
      p2_wait_last_extra |                          0101011 |                          0010011
       p2_fill_last_ifft |                          0101100 |                          0010100
       p2_wait_last_ifft |                          0101101 |                          0010101
            p2_insert_tr |                          0101110 |                          0001101
               p2_get_tr |                          0101111 |                          0001100
    p2_get_extra_pilot_2 |                          0110000 |                          0011010
 p2_insert_extra_pilot_2 |                          0110001 |                          0011011
    p2_get_extra_pilot_3 |                          0110010 |                          0011100
 p2_insert_extra_pilot_3 |                          0110011 |                          0011101
            p2_get_pilot |                          0110100 |                          0001110
         p2_insert_pilot |                          0110101 |                          0001111
      p2_insert_datacell |                          0110110 |                          0010000
       data_start_symbol |                          0110111 |                          0011110
   data_wait_interleaver |                          0111000 |                          0011111
          data_wait_ifft |                          0111001 |                          0100000
    data_fill_first_ifft |                          0111010 |                          0100001
      data_fill_pipeline |                          0111011 |                          0100010
  data_insert_first_edge |                          0111100 |                          0100011
     data_decide_carrier |                          0111101 |                          0100100
      data_get_last_edge |                          0111110 |                          0101100
   data_insert_last_edge |                          0111111 |                          0101101
     data_fill_last_ifft |                          1000000 |                          0101110
     data_wait_last_ifft |                          1000001 |                          0101111
          data_insert_tr |                          1000010 |                          0101010
             data_get_tr |                          1000011 |                          0101011
data_get_continual_scattered |                          1000100 |                          0100111
      data_get_continual |                          1000101 |                          0100101
      data_get_scattered |                          1000110 |                          0100110
       data_insert_pilot |                          1000111 |                          0101000
    data_insert_datacell |                          1001000 |                          0101001
         fc_start_symbol |                          1001001 |                          0110000
     fc_wait_interleaver |                          1001010 |                          0110001
            fc_wait_ifft |                          1001011 |                          0110010
      fc_fill_first_ifft |                          1001100 |                          0110011
        fc_fill_pipeline |                          1001101 |                          0110100
    fc_insert_first_edge |                          1001110 |                          0110101
       fc_decide_carrier |                          1001111 |                          0110110
            fc_get_pilot |                          1010000 |                          0110111
         fc_insert_pilot |                          1010001 |                          0111000
        fc_get_last_edge |                          1010010 |                          0111100
     fc_insert_last_edge |                          1010011 |                          0111101
       fc_fill_last_ifft |                          1010100 |                          0111110
       fc_wait_last_ifft |                          1010101 |                          0111111
        finish_ifft_load |                          1010110 |                          0000010
            fc_insert_tr |                          1010111 |                          0111010
               fc_get_tr |                          1011000 |                          0111011
      fc_insert_datacell |                          1011001 |                          0111001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'Symbol_Assembler'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                              000 |                              000
    wait_p1_start_encode |                              001 |                              001
      wait_p1_end_encode |                              010 |                              010
         wait_ifft_ready |                              011 |                              011
             start_frame |                              100 |                              100
        insert_p1_symbol |                              101 |                              101
         wait_symbol_end |                              110 |                              110
              symbol_end |                              111 |                              111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_out_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                            00000
         wait_s1_s2_data |                             0001 |                            00001
            wait_ifft_p1 |                             0010 |                            00010
        encode_p1_symbol |                             0011 |                            00011
        wait_p1_encoding |                             0100 |                            00100
               end_frame |                             0101 |                            00101
        wait_frame_start |                             0110 |                            00110
    get_frame_parameters |                             0111 |                            00111
           new_p1_t2base |                             1000 |                            01000
      assemble_p1_symbol |                             1001 |                            01001
           new_p2_symbol |                             1010 |                            01010
      assemble_p2_symbol |                             1011 |                            01011
         new_data_symbol |                             1100 |                            01100
    assemble_data_symbol |                             1101 |                            01101
           new_fc_symbol |                             1110 |                            01110
      assemble_fc_symbol |                             1111 |                            01111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_reg' using encoding 'sequential' in module 'T2_Framer'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                     Old Encoding 
---------------------------------------------------------------------------------------------------
                   reset |                             0000 |                             0000
                    idle |                             0001 |                             0001
            process_conf |                             0010 |                             0010
              process_l1 |                             0011 |                             0011
             process_plp |                             0100 |                             0100
           process_dummy |                             0101 |                             0101
             process_aux |                             0110 |                             0110
           process_unmod |                             0111 |                             0111
             process_fef |                             1000 |                             1000
              process_p1 |                             1001 |                             1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'estado_DMA_reg' using encoding 'sequential' in module 'T2_Framer'

Now, "L1_Preprocessor" doesn't appear in the report... So Vivado 2015.2 has the same bug... Vivado is one of the worse pains I've ever suffered...

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9,108 Views
Registered: ‎05-27-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

This really is strange.

 

It is almost as if a human did not write the synthesis tools.

 

Those who did should be able to list the *exact* conditions required for a FSM to be consistently inferred.

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Moderator
Moderator
9,091 Views
Registered: ‎07-21-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

@alexmoya

 

Without having access to the design files, we may not be able to comment on the reason behind this issue. Can you try running any Xilinx Example design and let us know if the same reporting is done by the tool or is there any way we can reproduce the same.

 

Thanks,
Anusheel
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Visitor lbenites
Visitor
7,106 Views
Registered: ‎08-15-2014

Re: [Vivado 2015.1] FSM encoding report is not complete!

I would strongly recommend that you open the synthesiszed schematic and look for the flops that hold the state for the FSM that isn't in the report. Then check to see if the D input of thoee flops are connecting to LUTs that have all the inputs to your FSM.

 

We have recently discovered what appears to be Vivado 2015 bugs that disconnect some/all the inputs to FSMs (previous version of Vivado work fine) So this may not be a simple reporting problem, but a BIGGER problem. If all the FSM input are there, then ignore this warning and carry on.

 

Luis

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Explorer
Explorer
5,194 Views
Registered: ‎11-23-2009

Re: [Vivado 2015.1] FSM encoding report is not complete!

@balkris wrote in Message 2 of this thread that fsm_extraction should be set to 'auto' to see encoding reports.

 

I've seen several statements in this direction, and imho they are not correct. One can use 'one_hot' as well, and one gets inference as well as encoding reports. As it should be. And by the way: fsm_extraction = one_hot is the setting choosen in the PerfOptimized_high synthesis strategy, would be bad if that screews up fsm inference.

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