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Explorer
Explorer
8,713 Views
Registered: ‎07-28-2008

Vivado 2015.4 Macro Defined in Verilog Header File Incurs Critical Warning

Same design source never had any warning messages in Vivado 2015.2.

 

Critical WARNING:

[HDL 9-870] Macro <SOME_MACRO> is not defined. [file_name.v:80]

[HDL 9-281] Cannot open include file "header.v". [file_name.v: 48]

 

I can see the header.v is under Design Source in folder "Verilog Header". Interesting thing is at the original state of project upgrading from 2015.2, the icon of the verilog header file is blue. Tried delete it once during troubleshooting, the file stays and icon changes to greenish.

 

Regardless these warnings, design synthesize without issue.

 

Any comments?

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4 Replies
Moderator
Moderator
8,707 Views
Registered: ‎07-01-2015

Re: Vivado 2015.4 Macro Defined in Verilog Header File Incurs Critical Warning

Hi @legendbb,

 

Can you see verilog header under non-module files?

It should be having green colour icon.

 

Also verify the property of that file.

Attaching snapshot for your refernce.

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
Moderator
8,692 Views
Registered: ‎01-16-2013

Re: Vivado 2015.4 Macro Defined in Verilog Header File Incurs Critical Warning

@legendbb,

 

It would be helpful if you can share the test case to replicate the issue.

Also try to set Global_Include property on Verilog header file and see if you are still seeing the same warning:

 

Capture.PNG

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
8,690 Views
Registered: ‎01-16-2013

Re: Vivado 2015.4 Macro Defined in Verilog Header File Incurs Critical Warning

@legendbb,

 

Check this AR#51164 on defining verilog macro in Vivado: 

http://www.xilinx.com/support/answers/51164.html

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
8,678 Views
Registered: ‎07-28-2008

Re: Vivado 2015.4 Macro Defined in Verilog Header File Incurs Critical Warning

Thanks for attention. I do have the same thing in your illustration.

The macro I used is actually for implementation.

An example snippet:

`define UNPACK_ARRAY(LOOP_IDX, PK_WIDTH, PK_LEN, PK_SRC, PK_DEST) \
  generate  \
    for (LOOP_IDX=0; LOOP_IDX<(PK_LEN); LOOP_IDX=LOOP_IDX+1) begin \
        assign PK_DEST[LOOP_IDX][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*LOOP_IDX+(PK_WIDTH-1)):((PK_WIDTH)*LOOP_IDX)]; \
    end \
  endgenerate
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