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Observer axio
Observer
459 Views
Registered: ‎07-13-2017

Vivado 2016.04 gating conversion failed

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Hi all,

There are lot of clock gating cell in our asic design.

ck_cell.JPG

 

I've already check on  the clock_gating_conversion option

gate_conv.JPG

 

However, the timing failed (hold violation) after implementation. I analyzed the path and found the gating cell conversion failed.

Here is the one snapshot of the failed path.

timing_path.JPG

 

The corresponding ck_cell synthesized schematic shows no conversion happens

ck_blk.JPG

 

Is there any conversion limitation by the vivado tools or my wrong timing constraints?

 

I just created the primary clock, ignore the constraints of the generated clock  modified by mmcm,bufg_gt etc.

 

btw.

the clock of the mentioned violation path comes from the output of BUFG_GT

 

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Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎09-24-2017

Re: Vivado 2016.04 gating conversion failed

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Hi @axio,

Please refer to 'GATED CLOCK'  section of  ug901.

Besides what you've done, you still need to add gated_clock attribute to the clock net in your RTL design. Example is as following:

 

GATED_CLOCK Example (Verilog)
(* gated_clock = “true” *) input clk;


GATED_CLOCK Example (VHDL)
entity test is port (
in1, in2 : in std_logic_vector(9 downto 0);
en : in std_logic;
clk : in std_logic;
out1 : out std_logic_vector( 9 downto 0));
attribute gated_clock : string;
attribute gated_clock of clk : signal is "true";
end test;

 

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Xilinx Employee
Xilinx Employee
436 Views
Registered: ‎09-24-2017

Re: Vivado 2016.04 gating conversion failed

Jump to solution

Hi @axio,

Please refer to 'GATED CLOCK'  section of  ug901.

Besides what you've done, you still need to add gated_clock attribute to the clock net in your RTL design. Example is as following:

 

GATED_CLOCK Example (Verilog)
(* gated_clock = “true” *) input clk;


GATED_CLOCK Example (VHDL)
entity test is port (
in1, in2 : in std_logic_vector(9 downto 0);
en : in std_logic;
clk : in std_logic;
out1 : out std_logic_vector( 9 downto 0));
attribute gated_clock : string;
attribute gated_clock of clk : signal is "true";
end test;

 

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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Observer axio
Observer
427 Views
Registered: ‎07-13-2017

Re: Vivado 2016.04 gating conversion failed

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Hi martinwe,

 

Thanks a lot. I change the gated_clock_conversion property to "auto", the tool can detect the gated clock automatically and make the conversion successfully. 

 

Br Ting

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