08-04-2017 07:18 PM
I have the following top-level definition:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all; use work.lnx1_types.all; use work.lnx1_cpu.all; entity intro_main is port ( clk_ext : in std_logic; irq_ext : in std_logic; data_ext : inout std_logic_vector(7 downto 0); addr_ext : out std_logic_vector(15 downto 0); en_db_drive_from_pt : out std_logic; clk_ram: out std_logic; rq_int_id: out std_logic; int_ack: out std_logic ); end intro_main; architecture Toplevel of intro_main is component lnx1_exec_core is port ( exec_core_in: in lnx1_exec_core_in; exec_core_out: out lnx1_exec_core_out; exec_core_inout: inout lnx1_exec_core_inout ); end component lnx1_exec_core; begin cpu0: lnx1_exec_core port map ( exec_core_in.clk => clk_ext, exec_core_in.irq => irq_ext, exec_core_out.addr => addr_ext, exec_core_out.cs.en_db_drive_from_pt => en_db_drive_from_pt, exec_core_out.cs.clk_ram => clk_ram, exec_core_out.cs.rq_int_id => rq_int_id, exec_core_out.cs.int_ack => int_ack, exec_core_inout.data => data_ext ); end architecture Toplevel;
To add constraints to the signals, I open the Timing Constraints Wizard. However, there was no entry present for the "clk_ram" signal.
Here you can see the missing signal from the list of output delays, namely the "clk_ram" signal::
The "ckl_ram" signal was not present on any page of the Timing Constraints Wizard, and thus a constraint for it was not generated.
Is this potentially due to being optimized away? This shouldn't be the case, as although I've verified the signal and asserted its connectivity, the program shouldn't be making assumptions as to what I could be connecting to that signal externally.
Note: I have already assigned actual pins to all the ports from the IO Planning interface before running this Wizard.
08-04-2017 09:40 PM
Chances are good that your clk_ram signal got renamed or removed, but to tell for sure the missing code for the lnx1_exec_core (and the packages) would be required.