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Participant
Participant
1,164 Views
Registered: ‎07-21-2016

Vivado 2017.1 incorrect optimization until wired to ILA

I have a custom IP core in Vivado.  There is logic within the core which is being optimized out.

 

The output from this logic is wired to output pins.

 

When I try to wire the Outputs to an ILA to debug, the logic is NOT optimized and the output pins from the FPGA work as designed.

 

Please find Verilog code attached for the core being optimized.

 

All pins are tied LOW in the case where it is optimized out.

 

 

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Mentor
Mentor
1,154 Views
Registered: ‎02-24-2014

Re: Vivado 2017.1 incorrect optimization until wired to ILA

There's nothing obviously wrong with your code here..  except for the fact that you are driving a global clock buffer with a register divider.    This creates clock domain crossings which are difficult to time properly.    You should be using a MMCM or PLL to generate the half rate clock, since this gives a half rate clock that's perfectly (mostly) aligned with your orginal clock.

 

Try loading the elaborated design  "Open Elaborated Design" and then check the connections from this module to the IO pins..  something must be wrong here.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Vivado 2017.1 incorrect optimization until wired to ILA

@aoliveri2

 

Do you see similar optimization even if the attached module is set as top? I believe the optimization is happening when you integrate the module in main design. Please confirm.

 

MARK_DEBUG attribute will force a DONT_TOUCH attribute on the signals and hence you are not seeing any optimization. To me this looks like a constant propagation related optimization, but its better to open the elaborated design and see whether the optimization is correct or not.

 

Thanks

Anusheel

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Participant
Participant
1,104 Views
Registered: ‎07-21-2016

Re: Vivado 2017.1 incorrect optimization until wired to ILA

Yes.  The optimization only occurs when integrated to the main design.  For example: simulation runs without issues.  

 

I am thinking it has something to do with the global buffer of the divided clock signal maybe as suggested.  I will rewrite the core using the divided signal as a clock enable instead and see what happens.

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Vivado 2017.1 incorrect optimization until wired to ILA

@aoliveri2

 

If you don't want to rewrite the code, then please go ahead with the DONT_TOUCH/MARK_DEBUG attribute. These attributes will stop the optimizations for these signals, but please have a look into the design to understand why tool decided to optimize it.

 

Thanks

Anusheel

 

 

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