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raghup17
Visitor
Visitor
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Registered: ‎03-26-2014

Vivado 2017.1 register retiming usage

I am trying to use the retiming feature in Vivado (2017.1) to retime a divide operation. The target board is the Zynq ZC706.

The Verilog looks like this:

 

module AccelTop( ...);

...

  reg[31:0] sr1, sr2, sr3, sr4, sr5, sr6, sr7, sr8, sr9, retimed_out;

 

  assign num1 = $signed(input1);   // 32-bit input from memory-mapped register file
  assign num2 = $signed(input2);  // 32-bit input from memory-mapped register file
  assign out = $signed(num1) / $signed(num2);

  always @(posedge clk) begin

    sr1 <= out;
    sr2 <= sr1;
    sr3 <= sr2;
    sr4 <= sr3;
    sr5 <= sr4;
    sr6 <= sr5;
    sr7 <= sr6;
    sr8 <= sr7;
    sr9 <= sr8;
    retimed_out <= sr9;

  end

endmodule

 

This logic is inside a module that is instantiated within the Top module of the design. I am using the TCL scripts in Vivado project mode to synthesize and implement this design, with a target clock frequency of 50 MHz. I'm observing two things:

1. I fail to meet timing whether or not retiming is enabled, with EXACTLY the same negative slack (-25.97ns).

2. The synthesis report shows that the above shift register is being implemented using SRL* primitives, indicating that it was not used for retiming.

3. In the synthesis report, the module above (AccelTop) does not seem to be considered for retiming. Specifically, I see the following lines:

 

INFO: [Synth 8-5816] Retiming module `design_1_axi_mem_intercon_0`
No candidate paths found in current hierarchy level
Skipping retiming for this module
INFO: [Synth 8-5816] Retiming module `design_1_axi_mem_intercon_0' done
INFO: [Synth 8-5816] Retiming module `design_1_ps7_0_axi_periph_0`
No candidate paths found in current hierarchy level
Skipping retiming for this module
INFO: [Synth 8-5816] Retiming module `design_1_ps7_0_axi_periph_0' done
INFO: [Synth 8-5816] Retiming module `design_1`
No candidate paths found in current hierarchy level
Skipping retiming for this module
INFO: [Synth 8-5816] Retiming module `design_1' done
INFO: [Synth 8-5816] Retiming module `design_1_wrapper` No candidate paths found in current hierarchy level
Skipping retiming for this module
INFO: [Synth 8-5816] Retiming module `design_1_wrapper' done

 

I have attached the reproducing test case along with the TCL build scripts and Makefile. The relevant Verilog is in 'AccelTop.v'.

To reproduce, simply type 'make'. 

 

I have already seen other posts on this issue, and they have not been helpful. I would appreciate any help / guidance from Xilinx and other forum members on the usage of retiming here. 

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muzaffer
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Teacher
2,906 Views
Registered: ‎03-31-2012

@raghup17 retiming happens later than register storage inference probably. Did you try to for register type to the srX registers? or disallow SRL on them? Try https://www.xilinx.com/support/answers/53956.html

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