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Vivado 2018.1 IP module not found in mixed language design with VHDL 2008

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Visitor
Posts: 2
Registered: ‎05-11-2018

Vivado 2018.1 IP module not found in mixed language design with VHDL 2008

I found a bug with IP instatination in mixed-language project.

 

Simple design structure:

 

top (SystemVerilog)

   vhdl_wrapper(VHDL 2008)

       scfifo_wrapper_us(SystemVerilog)

           sc_fifo_8x512( Xilinx IP - FIFO generator v13.2)

 

If vhdl_wrapper.vhd file has type VHDL 2008 then synthesis returns with error:

[Synth 8-439] module 'sc_fifo_8x512' not found ["/vivado_bug/scfifo_wrapper_us.sv":24]

 

If I switch vhdl_wrapper.vhd type to VHDL then synthesis finishes without errors.

 

This bug also can be seen in Hierarchy view in Sources window. 

 

Attached test case so you can reproduce bug, project is called vivado_bug. I've tested it only on linux version. In Vivado 2017.4 everything is OK.

         

Moderator
Posts: 242
Registered: ‎02-07-2008

Re: Vivado 2018.1 IP module not found in mixed language design with VHDL 2008

Hi @k.rymarz, thanks for raising this issue and for uploading the test case. This issue has been fixed in 2018.2 (see uploaded v2018.2.log).

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Visitor
Posts: 2
Registered: ‎05-11-2018

Re: Vivado 2018.1 IP module not found in mixed language design with VHDL 2008

Hi @peadard,

 

Can you provide me information when 2018.2 will be available? 

Moderator
Posts: 511
Registered: ‎03-16-2017

Re: Vivado 2018.1 IP module not found in mixed language design with VHDL 2008

Hi @k.rymarz,

 

Vivado 208.2 is available. 

 

You can get it from xilinx.com\download 

 

Regards,

hemangd