06-13-2018 05:33 AM
I found a bug with IP instatination in mixed-language project.
Simple design structure:
sc_fifo_8x512( Xilinx IP - FIFO generator v13.2)
If vhdl_wrapper.vhd file has type VHDL 2008 then synthesis returns with error:
[Synth 8-439] module 'sc_fifo_8x512' not found ["/vivado_bug/scfifo_wrapper_us.sv":24]
If I switch vhdl_wrapper.vhd type to VHDL then synthesis finishes without errors.
This bug also can be seen in Hierarchy view in Sources window.
Attached test case so you can reproduce bug, project is called vivado_bug. I've tested it only on linux version. In Vivado 2017.4 everything is OK.
06-13-2018 06:13 AM
Hi @k.rymarz, thanks for raising this issue and for uploading the test case. This issue has been fixed in 2018.2 (see uploaded v2018.2.log).