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Observer nikhenri
Observer
507 Views
Registered: ‎05-15-2013

Vivado 2018.1 VHDL-2008 : Slices in Array Aggregates doesn't work correctly

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Seem there is an issue with Vivado 2018.1 and Slices in Array Aggregates.

In VHDL-2008, you can put array in aggregates, the synthesis tool doesn't see any syntax error (good) but see a false synthesis error. The problem is that Vivado think the length of an item in aggregate is always equal to 1 (false for VHDL2008, you can put array in aggregates).

 

code:

    b <= (b(b'high-1 downto 0),c); --Synthesis error "[Synth 8-690] width mismatch in assignment; target has 4 bits, source has 2 bits"
   -- b <= b(b'high-1 downto 0) & c; --WORK

As you can see, the size are correct since the second line work, which mean Vivado have some difficulty estimate the length of an aggregate.

 

I have put in attachments a print screen and a code example

 

Capture_aggregate.JPG
1 Solution

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Xilinx Employee
Xilinx Employee
468 Views
Registered: ‎02-16-2014

Re: Vivado 2018.1 VHDL-2008 : Slices in Array Aggregates doesn't work correctly

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Hi @nikhenri

 

Thanks for reporting this issue. Reproduced and filed CR for this issue.

 

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Scholar jmcclusk
Scholar
491 Views
Registered: ‎02-24-2014

Re: Vivado 2018.1 VHDL-2008 : Slices in Array Aggregates doesn't work correctly

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This has been an ongoing issue for years with Vivado synthesis.    I'm wondering if a CR exists for this problem.

Don't forget to close a thread when possible by accepting a post as a solution.
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Xilinx Employee
Xilinx Employee
469 Views
Registered: ‎02-16-2014

Re: Vivado 2018.1 VHDL-2008 : Slices in Array Aggregates doesn't work correctly

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Hi @nikhenri

 

Thanks for reporting this issue. Reproduced and filed CR for this issue.

 

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