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patcher33
Participant
Participant
749 Views
Registered: ‎02-01-2018

Vivado 2018.2.1: use_dsp problems with three inputs

Hello,

there is a simple test design, that implements three adders and should fit into three DSP48. use_dsp is used to force DSP48 blocks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity use_dsp_bug is
    Port ( clk : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR (47 downto 0);
           b : in STD_LOGIC_VECTOR (47 downto 0);
           c : in STD_LOGIC_VECTOR (47 downto 0);
           d : in STD_LOGIC_VECTOR (47 downto 0);
           res : out STD_LOGIC_VECTOR (47 downto 0)
           );
end use_dsp_bug;

architecture Behavioral of use_dsp_bug is
signal res1,res2,res3: STD_LOGIC_VECTOR (47 downto 0);

attribute use_dsp : string;
attribute use_dsp of res1,res2,res3 : signal is "yes";

begin
    res<=res3;
    process(clk) 
    begin
        if rising_edge(clk) then
            res1<=a+b; -- OK: first DSP48 adder with two inputs
            res2<=c+res1+res1; -- BUG1: need 2 DSP48 
            --res3<=d+res2+res1; -- BUG2: use 2x DSP48 and depends on the write order of res3 operands
            res3<=res2+res1+d; -- OK: use 1x DSP48 adder with three inputs
        end if;
    end process; 
end Behavioral;

Problem 1: res2 need in all cases TWO DSP48 blocks. It should possible to use P->A:B, PCOUT->PCIN and C connections, but the synthesis tool makes two DSP48 modules instead:

res3=res2+res1+d.PNG

It becomes more interresting, if the order of the res3 arguments will be changed:

        if rising_edge(clk) then
            res1<=a+b; -- OK: first DSP48 adder with two inputs
            res2<=c+res1+res1; -- BUG1: need 2 DSP48 
            res3<=d+res2+res1; -- BUG2: use 2x DSP48 and depends on the write order of res3 operands
            --res3<=res2+res1+d; -- OK: use 1x DSP48 adder with three inputs
        end if;

Now also res3 will be implemented by TWO DSP48. At all: FIVE DSP48 instead of required THREE!

res3=d+res2+res1.PNG

Is it a bug or a feature?

 

Regards

 

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2 Replies
hemangd
Moderator
Moderator
733 Views
Registered: ‎03-16-2017

Hi @patcher33 ,

You can use -max_dsp = 3 switch which will set the limit for the tool to use DSP. You can set it from synthesis settings. 

Though it will reflect in usage of LUT and flops. 

Regards,
hemangd

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patcher33
Participant
Participant
727 Views
Registered: ‎02-01-2018

Hi @hemangd,

max_dsp = 3 limits the TOTAL number of DSP48 in the WHOLE design and as you wrote pushes the rest of the calc into fabric. It is not a solution for the real application.

 

 

 

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