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Observer richw42a
Observer
730 Views
Registered: ‎03-05-2014

Vivado 2018.2 FSM Problem

I'm having trouble with an FSM (finite state machine) that seems to behave contrary to my code. The symptoms keep changing when, for example, I put a (* KEEP = "TRUE" *) on my state variable, or delete it. Below is what I believe is a clear evidence of misbehavior. Starting from state 0 (st_idle), when the go condition becomes true, we transition to state 1 (st_1). The signal crc7_clear goes true as one would expect, but the signal crc7_go also goes true, which should not happen until exiting from state 1. crc7_go seems to occur one clock early. This makes it difficult to calculate the correct crc :)

Note in the code evidence of a previous battle with the synthesizer. The shift signal was changing on exit from st_1, so I added a redundant setting for shift.

I'm at a loss for what to do next. 

 

 

Capture.PNG

 

 

	    case (state)
		st_idle:
		begin
		    if (go)
		    begin
			active <= 1;
			serror <= 0;
			clock_go <= 1;
			if (my_task == task_cmd ||
			    my_task == task_cmd_reg ||
			    my_task == task_cmd_long_reg ||
			    my_task == task_write ||
			    my_task == task_read ||
			    my_task == task_cmd_reg_data)
			begin
			    state <= st_1;
			    drive_cmd <= 1;
			    cnt_bits <= 9'd7;	// Send 8 bits
			    sd_cmd_out <= 1;
			    // Start and transmit bits followed by command index
			    shift <= { 2'b01, sd_cmd_index, 24'h0 };
			    crc7_clear <= 1;
			end
			else if (my_task == task_write_m)
			begin
...
end else if (my_task == task_read_m) begin
... end end end st_1: // Getting ready to output cmd if (clock_fall_in_2) begin // Sync to sd clock state <= st_2; // Kludge since the synthesizer seemed to make a mistake shift <= { 2'b01, sd_cmd_index, 24'h0 }; crc7_go <= 1; // Calculate CRC before shift[31] gets corrupted end

 

 

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10 Replies
Moderator
Moderator
667 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

Can you provide the RTL source file to evaluate it or end?

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer richw42a
Observer
660 Views
Registered: ‎03-05-2014

Re: Vivado 2018.2 FSM Problem

Is the code for that one module enough to evaluate? Or do you need the entire design?

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Moderator
Moderator
657 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

You can provide a testcase (archived project) using which i can see the functionality as you stated in post synthesis functional simulation. 

 

I have sent you ezmove ftp , where you can provide the files. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer richw42a
Observer
655 Views
Registered: ‎03-05-2014

Re: Vivado 2018.2 FSM Problem

The failures occurred with real hardware. I will need to reproduce the problem with simulation, and then I'll send it along.

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Moderator
Moderator
653 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

Sure, i will recommend you to check behavioral simulation and post-synthesis functional simulation and let us know if you see any functionality difference as per your expectations. - This is the recommended way to check the functionality of your code is correct or not before dumping it on to the board. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Moderator
Moderator
633 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

Any updates you would like to share on this issue?


Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer richw42a
Observer
623 Views
Registered: ‎03-05-2014

Re: Vivado 2018.2 FSM Problem

What between working remotely, silly mistakes, Vivado crashing, the  analyzer not cooperating, Comcast dropping out, and other impediments, I think we are at the point of maximum confusion. If things ever start making sense again, and we again see FSM misbehavior, I'll be back.

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Moderator
Moderator
554 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

Do you have any updates to share on this thread? 

 

If no, you may close it temporarily by marking it as accepted solution. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer richw42a
Observer
503 Views
Registered: ‎03-05-2014

Re: Vivado 2018.2 FSM Problem

I think the problem was creating an ila debug session using the Vivado "Set Up Debug" GUI. Apparently the synthesizer sees a state machine and does aggressive optimizations without changing the names of the signals. Thus, when I'm trying to debug my FSM, nothing makes sense, even though the FSM is doing exactly what I asked it to do, as far as normally externally visible signals are concerned.

The solution was to use the ILA Debug IP to create the debug session. Now the synthesizer sees a signal going into an already synthesized box, and is forced to keep the same visible behavior on any signals connected to the ILA.

Perhaps an equivalent solution would be to mark all signals involved in debug with KEEP attributes, and use the Vivado "Set Up Debug" GUI.

Perhaps there is a Fine Manual somewhere that explains all this :)

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Moderator
Moderator
467 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 FSM Problem

Hi @richw42a,

 

Yes, you can also try to apply don't touch attribute on the debug signals. 

To know more on these attributes, FSM inferrence - you may check UG 901 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf

Chapter 2 & 4.

 

Regards,

hemangd

If your issue has been resolved, then you may close thread by marking it as accepted solution. 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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