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jarios86
Contributor
Contributor
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Registered: ‎10-18-2015

Vivado 2018.2 synthesis crashes on Technology Mapping

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Hi everyone,

I have experienced a problem when I try to synth my RTL design. The synth process always fails in the same point "Start Technology Mapping". I have used several synth strategies, including the default one, but it always crashes. The message that I get in the synth log is the following one:

---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
/opt/Xilinx/Vivado/2018.2/bin/loader: line 194: 11530 Killed "$RDI_PROG" "$@"
Parent process (pid 11530) has died. This helper process will now exit
pure virtual method called
terminate called without an active exception

I have tried the solution posted in this the following link, but it doesn't work.

https://www.xilinx.com/support/answers/64434.html

Attached you can find the synth log file. I'll appreciate any kind of help.

Best,
Antonio

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jarios86
Contributor
Contributor
968 Views
Registered: ‎10-18-2015

Hi everyone,

After sending my project to @pulim and follow his recommendations the problem is solved. I increased the virtual memory of my system to 32GB and now the synthesis process works fine. Sometimes, increasing the stack memory of vivado is not enough, we need to increase the virtual memory of our system.

Thanks @pulim for your efforts,

Best,
Antonio

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pulim
Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Hi @jarios86 

Have you tried with -flatten_hierarchy none option and do you still see same crash?

I see that you are using 2018.2, Can you try with latest version of vivado 2019.2 and if you still see this crash?

Do you see any hs_err_pid*.log file being created in synthesis run folder?

If possible please share project to check and debug at my end.

 

Thanks,

Manusha

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jarios86
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1,125 Views
Registered: ‎10-18-2015

Hi @pulim,

Thanks for your prompt response. Yes, I've tried with -flatten_hierarchy none option, but it still crashes. Now the error is a bit different but it still crashes:

/opt/Xilinx/Vivado/2018.2/bin/loader: line 194: 19556 Killed "$RDI_PROG" "$@"
Parent process (pid 19556) has died. This helper process will now exit
vivado: /proj/rdi-xco/wall/workspaces/wall401/sub/REL/2018.2/src/ext/oasys/src/db/tim/TGenDelay.cc:519: TGenDelayTmp* TGenDelayTmp::addSetup(TGenDelayTmp*, int, TGenChar*, TMode*): Assertion `TBD' failed.

Attached you can fin the files hs_err_pid*.log that are generated under synthesis run folder.

Yes, I'm using vivado 2018.2 because my project is under this version and the petalinux project associate to this vivado project is in the same version too. If I change the vivado version I should change all the tool-chain version. Anyway, I'm going to install the vivado 2019.2 in order to see if this solve the problem.

Please, let me know if you see any hint to solve the problem from the hs_err_pid*.log files. I'll appreciate it so much.

Thanks,
Antonio

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pulim
Xilinx Employee
Xilinx Employee
1,075 Views
Registered: ‎02-16-2014

Hi @jarios86 

 

Thanks for sharing crash dumpfiles.

I see that attached 3 crash dump files are not same. Everytime tool crashed it might be generating different crash dump files.

But from the crash dump it looks to be related to timing constraints.

Can you see if there are critical warnings related to timing constraints are provided in vivado log file?

To debug this issue, can you try disabling your xdc file for synthesis and see if it still crashes?

Are you using any BLOCK_SYNTH properties in your design?

If you have any possibility to share your design to debug further, please let me know I can send you secured ezmove link with which you can share files.

 

Thanks,

Manusha

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jarios86
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1,048 Views
Registered: ‎10-18-2015

Hi @pulim 

Thanks for your response and your comments and suggestions.

I've checked the vivado log file and I have not seen any critical warnings related to timing constraints. I have not timing constraints in my xdc files, but I've disabled them to run the synth, but it still crashes. I'm not using any BLOCK_SYNTH properties in my design.

In my last synth attempt, disabling all my xdc files I got this error:

/opt/Xilinx/Vivado/2018.2/bin/loader: line 194: 29833 Killed "$RDI_PROG" "$@"
Parent process (pid 29833) has died. This helper process will now exit
ERROR: [Device 21-408] ERROR: Failed to load veamMap: No such belRef pcie4_pcie4_core_0:PCIE40E4/PCIE40E4 in tileType PCIE4_PCIE4_FT
at line 87568 in /opt/Xilinx/Vivado/2018.2/data/parts/xilinx/zynquplus/devint/zynquplus/zynquplus.veamMap. Most likely, you need to check your installation or recompile your sandbox.

If you tell me how can I share with you my project using a secured ezmove link, I'll comprise my project folder and share with you.

Thanks for your efforts and help.
Antonio

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pulim
Xilinx Employee
Xilinx Employee
1,036 Views
Registered: ‎02-16-2014

Hi @jarios86 

Sent you private message. Please check.

Thanks,

Manusha

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jarios86
Contributor
Contributor
969 Views
Registered: ‎10-18-2015

Hi everyone,

After sending my project to @pulim and follow his recommendations the problem is solved. I increased the virtual memory of my system to 32GB and now the synthesis process works fine. Sometimes, increasing the stack memory of vivado is not enough, we need to increase the virtual memory of our system.

Thanks @pulim for your efforts,

Best,
Antonio

View solution in original post

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