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Contributor
Contributor
723 Views
Registered: ‎04-26-2015

Vivado 2018.2 synthesis failed without error

 

Hi

Recently I have installed Vivado 2018.2 (Webpack) in my workstation, when I was trying to synthesis a very simple RTL.

It shows status: synth_design ERROR, but no errors are generated in the messages window.

However in the RTL analysis (inside Flow Navigator) I am able to see the schematic properly.

So what could be possible source of error as the code is written fine as given below (in Italic).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tri is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
c : out STD_LOGIC_VECTOR (2 downto 0));
end tri;

architecture Behavioral of tri is

begin

c <= a and b;

end Behavioral;

Thanks & regards

Madhur

Design run.PNG
Project summary.PNG
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11 Replies
Scholar drjohnsmith
Scholar
699 Views
Registered: ‎07-09-2009

Re: Vivado 2018.2 synthesis failed without error

There will be a message , probably in the TCL window , but basicaly you have bad VHDL, you need a process in there, else its and empty entity.

Try

architecture Behavioral of tri is

begin

mb : process( a,b )

begin

c <= a and b;

end process mb;

end Behavioral;

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
684 Views
Registered: ‎04-26-2015

Re: Vivado 2018.2 synthesis failed without error

Hello drjohnsmith

I think that's not issue with the code, what I have written is the concurrent statement.

And as already mentioned in my original post, I am already getting the schematic being generated. (attached for reference) from the same code.

As far as Messages are concerned, snapshot of TCL console and messages are attached below.

regards

Madhur

schematic.PNG
tcl_console.PNG
messages.PNG
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Scholar drjohnsmith
Scholar
664 Views
Registered: ‎07-09-2009

Re: Vivado 2018.2 synthesis failed without error

I only have ISE to hand today,

   but this passes just fine

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tt_t is
    Port ( a : in  STD_LOGIC_VECTOR (2 downto 0);
           b : in  STD_LOGIC_VECTOR (2 downto 0);
           c : out  STD_LOGIC_VECTOR (2 downto 0));
end tt_t;

architecture Behavioral of tt_t is

begin

    c <= a and b;

end Behavioral;

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
659 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 synthesis failed without error

Hi @mjuneja ,

This is a machine specific issue. 

Run your testcase in another directory and make sure it has all the permission to write and read and modify. 

 

If it does not help, then run "report_environment -file <filepath>/env.txt" in tcl console and provide env.txt to evaluate. To check which file path run pwd.

 

 

Regards,
hemangd

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Contributor
Contributor
629 Views
Registered: ‎04-26-2015

Re: Vivado 2018.2 synthesis failed without error

Hi @hemangd 

Please check the attached env.txt file and suggest the possible solution..

Thanks 

 

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Moderator
Moderator
611 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 synthesis failed without error

@mjuneja 

Can you attach the synthesis log file here? That may help us to understand better what went wrong at your end.

Thanks
Anusheel

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Moderator
Moderator
607 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 synthesis failed without error

Hi @mjuneja ,

Turn off your anti virus temporarily and run synthesis. 

 

Also your APPDATA path contains whitespace - APPDATA=C:\Users\Madhur Juneja\AppData\Roaming

Remove that white space and restart your machine and then run synthesis.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Contributor
Contributor
598 Views
Registered: ‎04-26-2015

Re: Vivado 2018.2 synthesis failed without error

Hi @hemangd 

After disabling the antivirus, still the synthesis failed with no errors and warnings..as well as the progress halts at 0%.

However this time I have opened Vivado by running vivado.bat in location C:\Xilinxv\Vivado\2018.2\bin.

After synthesis failed, in the command window I am getting <project_path>synth_1\rundef.js<25,1> WshShell.Exec: Access is denied.

@anusheel Certain attachments from synth_1 folder is attached for your reference.

Thanks 

Madhur

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Moderator
Moderator
586 Views
Registered: ‎03-16-2017

Re: Vivado 2018.2 synthesis failed without error

Hi @mjuneja ,

 

Move your project or create a new project on directory where you have full access and write/modify permissions. Otherwise you will endup with the similar issue. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Moderator
Moderator
563 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 synthesis failed without error

@mjuneja 

synth_design was not even called when the crash occurred. Looks like permission issue as already mentioned. 
Also, try to reinstall Vivado if you have all the permissions and still tool/machine does not allow synthesis to complete.

Thanks
Anusheel 

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Contributor
Contributor
548 Views
Registered: ‎04-26-2015

Re: Vivado 2018.2 synthesis failed without error

@anusheel 

Actually as far as permission is concerned I am already logged in as administrator.

Initially I was working on Vivado 2018.2 where I was facing this isssue, but after uninstalling this version and installing the latest version Vivado 2018.3 situation has changed.

Now synthesis is not stopping at all (for the same code already shared in the original post) and it's been more than 12 hours since I started the synthesis run.

No message or warning is being shown in the TCL window and progress stuck at 0%.

However in the command window I am seeing the same error earlier reported.

"<project_path>\<project_name>.runs\synth_1\rundef.js<25,1> WshShell.Exec: Access is denied."

Somehow I am able to correlate this error with

https://forums.xilinx.com/t5/Synthesis/SYNTHESis-DOEsN-T-START/td-p/537407

But I am not able to crack this issue yet.

Script files rundef.js and ISEWrap.js are attached for your reference, and both these files are same in project folder as well as in Vivado script folder.

And my antivirus has not quarantined any of these script file.

Thanks & regards

Madhur

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