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Explorer
Explorer
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Registered: ‎07-10-2013

Vivado 2018.3 Support For System Verilog Wildcard Equality Operators

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UG901 (v2018.3) indicates in Table 8-1 on p.276 that wildcard equality operators are supported.  Where are such operators explicitly listed/referenced in the document?  Note that they appear to not be present under Operators on p.266.

What text character sequences are used to specify such operators (e.g., =?= and ==? (as seen from an Internet search) are clearly incorrect)?

Where can the System Verilog documentation/reference used in formulating Vivado support for System Verilog be found?

 

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Xilinx Employee
Xilinx Employee
195 Views
Registered: ‎05-22-2018

Re: Vivado 2018.3 Support For System Verilog Wildcard Equality Operators

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Hi @chsdkj,

I think the one which one which are mentioned in System Verilog LRM are the supported one's.

Regards,

Raj.

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Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎05-22-2018

Re: Vivado 2018.3 Support For System Verilog Wildcard Equality Operators

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Hi @chsdkj,

I think the one which one which are mentioned in System Verilog LRM are the supported one's.

Regards,

Raj.

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