01-20-2019 03:07 PM
UG901 (v2018.3) indicates in Table 8-1 on p.276 that wildcard equality operators are supported. Where are such operators explicitly listed/referenced in the document? Note that they appear to not be present under Operators on p.266.
What text character sequences are used to specify such operators (e.g., =?= and ==? (as seen from an Internet search) are clearly incorrect)?
Where can the System Verilog documentation/reference used in formulating Vivado support for System Verilog be found?