UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor ymherklotz
Visitor
329 Views
Registered: ‎06-06-2019

Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Hi,

There seems to be a mismatch between the synthesised net list and the initial design with the following Verilog code. This happens with Vivado 2019.1 on my personal arch linux machine and Vivado 2018.2 on CentoOS 6. I have attached all the necessary files to run it and hopefully reproduce it, together with a testbench that dumps a vcd file.

I have reduced the Verilog as much as possible, and changing anything else makes Vivado synthesise correctly.

module top (y, clk, w0);
   output [1:0] y;
   input clk;
   input [1:0] w0;
   reg [2:0] r1 = 3'b0;
   reg [1:0] r0 = 2'b0;
   assign y = r1;
   always
     @(posedge clk) begin
        r0 <= 1'b1;
        if (r0) r1 <= r0 ? w0[0:0] : 1'b0;
        else r1 <= 3'b1;
     end
endmodule

For an input of w2 = 2b'10 for two clock cycles, the final output should be 2'd0, because the if statement is entered on the second clk cycle and the lsb of w0 is assigned to r1, which is 1'b0.

However, with Vivado the output seems to be 2'10 instead, which seems like Vivado does not truncate the value of the input to the lsb in w0[0:0].

Expected output after 2 clock cycles with 2'b10 as input: 2'b00

Actual output: 2'b10

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
294 Views
Registered: ‎02-16-2014

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Hi @ymherklotz 

I am able to reproduce this issue at my end and filed CR to fix this issue in future releases.

As w1[1] is unused, declaring w1 as single bit can be used as workaround to move forward with design.

Hope this helps.

 

Thanks,

Manusha

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
295 Views
Registered: ‎02-16-2014

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Hi @ymherklotz 

I am able to reproduce this issue at my end and filed CR to fix this issue in future releases.

As w1[1] is unused, declaring w1 as single bit can be used as workaround to move forward with design.

Hope this helps.

 

Thanks,

Manusha

0 Kudos
Visitor ymherklotz
Visitor
289 Views
Registered: ‎06-06-2019

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Great thank you! That works.

0 Kudos
Scholar markcurry
Scholar
271 Views
Registered: ‎09-16-2009

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Does this bug affect any priori Vivado versions.  i.e. 2018.*?

This looks to me to be a rather critical bug.  @ymherklotz  - did you try your test on any other Vivado version?

@pulim are there any other details available on what triggers this bug?  Only in Vivado 2019?  Or others too?

Regards,

Mark

 

0 Kudos
Visitor ymherklotz
Visitor
266 Views
Registered: ‎06-06-2019

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

@markcurry, I have managed to reproduce this with 2016.2, 2017.4, 2018.2 and 2019.1, so it seems to be present in all those versions. Maybe @pulim can give more details though.

All the best,

Yann

0 Kudos
Xilinx Employee
Xilinx Employee
237 Views
Registered: ‎02-16-2014

Re: Vivado 2019.1 Bit selection synthesis mismatch

Jump to solution

Hi @markcurry 

 

Yes, This issue is there from atleast 2017.1.

I can give you more details once I get update on this CR.

0 Kudos