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Observer
Observer
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Registered: ‎05-10-2018

Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Is hierarchical signal access not supported for synthesis?

I am trying to re-organize my code by placing the ILA cores in the top level. Hierarchical references to lower levels of the design are made and assigned to ILA inputs. I get an error for each reference.

Below is an example of what I'm talking about. The error would occur at the assignment during RTL elaboration.

module top(...);

module_name module_name_instance(
    ....
);

byte data;

assign data = module_name_instance.internal_data;

endmodule

If this isn't supported is there any plan to add support? 

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Hierarchical naming is not supported and currently there is no plan to support it.

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Observer
Observer
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Registered: ‎05-10-2018

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Any reason why? It's a valid language construct after all.

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Observer
Observer
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Registered: ‎05-10-2018

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Page 238 AND 284 of UG901 lists "hierarchical names" as "Supported." 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

It seems that it has been this way for a few versions now. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2018

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Hi @dpikul ,

Hierarchical referencing is supported. Could you post snippet of code ?  Also do you have module for "module_name_instance" compiled/added ?

For example, please check snapshot.

 

Thanks,

Ajay

 

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Hi, @dpikul ,

I refer to the roadmap page out-of-date, and in current Vivado synthesis tool Hierachical naming is supported.

Sorry for the confusing.

All the hierachical name used in the source code should be defined by the user.  

 

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Observer
Observer
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Registered: ‎05-10-2018

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Ajay,

The snippet I posted is very similar to my code just with names obfuscated.

The entire design currently goes through implementation and runs on hardware, the build will not go through elaboration though if I use hierarchical referencing.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2018

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

Hi @dpikul ,

It could help if you can share design to get better idea.

Thanks,

Ajay

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Xilinx Employee
Xilinx Employee
104 Views
Registered: ‎05-14-2008

Re: Vivado 2019.1 Elaboration : ERROR: Cannot resolve hierarchical name for the item 'MODULE_NAME_INSTANCE'

assign data = module_name_instance.internal_data;

"module_name_instance" cannot be the current module itself.

For example

module aaa (...);

wire data;

assign data = bbb.internal_data;

bbb  my_inst (...);

endmodule

 

Just have a try.

-vivian

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