02-20-2020 02:30 PM
Is hierarchical signal access not supported for synthesis?
I am trying to re-organize my code by placing the ILA cores in the top level. Hierarchical references to lower levels of the design are made and assigned to ILA inputs. I get an error for each reference.
Below is an example of what I'm talking about. The error would occur at the assignment during RTL elaboration.
module top(...); module_name module_name_instance( .... ); byte data; assign data = module_name_instance.internal_data; endmodule
If this isn't supported is there any plan to add support?
02-21-2020 01:22 AM - edited 02-21-2020 02:01 AM
Hierarchical naming is not supported and currently there is no plan to support it.
02-21-2020 08:07 AM
Any reason why? It's a valid language construct after all.
02-21-2020 08:18 AM
Page 238 AND 284 of UG901 lists "hierarchical names" as "Supported."
It seems that it has been this way for a few versions now.
02-23-2020 09:58 PM
02-24-2020 12:17 AM - edited 02-25-2020 11:47 PM
Hi, @dpikul ,
I refer to the roadmap page out-of-date, and in current Vivado synthesis tool Hierachical naming is supported.
Sorry for the confusing.
All the hierachical name used in the source code should be defined by the user.
02-25-2020 01:32 PM
The snippet I posted is very similar to my code just with names obfuscated.
The entire design currently goes through implementation and runs on hardware, the build will not go through elaboration though if I use hierarchical referencing.
03-05-2020 02:54 AM
03-05-2020 07:28 PM
assign data = module_name_instance.internal_data;
"module_name_instance" cannot be the current module itself.
module aaa (...);
assign data = bbb.internal_data;
bbb my_inst (...);
Just have a try.