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mfrancis
Observer
Observer
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Registered: ‎07-04-2018

Vivado 2019.1: Ultrasclae+ architecture; Can Not map two SRL16 into a single LUT

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Hi

from UG 474 it states you can put two SRL16 into one LUT i.e 2 bits per LUT. At present while using a SRL16E component and having it in a For Generate Loop it is using 1 bit per LUT. Hence double resources. The address, clokc and enable are common. 

in my code hwoever the a register output goes to two different SRL16 chains. Could this be the cause of my issue?

 

regards

 

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @mfrancis ,

Please try the below example XDC to pack the 2 SRLs into 1 LUT.

set_property LUTNM L0 [get_cells {SRL16E_inst_1 SRL16E_inst_2}]

 

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hongh
Moderator
Moderator
654 Views
Registered: ‎11-04-2010

Hi, @mfrancis ,

Please try the below example XDC to pack the 2 SRLs into 1 LUT.

set_property LUTNM L0 [get_cells {SRL16E_inst_1 SRL16E_inst_2}]

 

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mfrancis
Observer
Observer
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Registered: ‎07-04-2018

Hi 

thanks for the reply. as an alternative  I put the SRl16E into its own file and called up the component at the next level.

 I_Data_inst : entity work.srl16_16bit
port map(
Sample_In_Data => I_Data_Cascade_In(j),
Sample_Clock => Sample_Clock,
Filter_A_Data_A_Select => Filter_A_Data_Select(j),
Sample_In_Valid => Sample_In_Valid,
Sample_Out_Data => I_Data(j)
);

that seemed to sort that out as well. see if you agree. if iso then we have two solutions.

 

 

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