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Visitor ymherklotz
Visitor
238 Views
Registered: ‎06-06-2019

[Vivado 2019.1] Unsigned bit extension in if statement

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Hi,

The code below does not seem to behave properly after synthesis with Vivado 2019.1. When the input to the module is w1 = 2'b01, then the output should be 0. This is because the unsigned literal -1'b1 in the if statement is zero extended to 2 bits giving -2'b01 = 2'b11.

As 2'b11 != w1 (which is 2'b01), r1 should never be set.

However, instead of 0, after synthesis with Vivado, the output it 1. This seems to have something to do with the concatenation as well, as if that is removed, Vivado synthesis works as expected and performs the right zero extension.

Assigning r1 directly to {-1'b1 == w1} also works as expected.

module top (y, clk, w1);
   output   y;
   input    clk;
   input signed [1:0] w1;
   reg                r1 = 1'b0;
   assign y = r1;
   
   always @(posedge clk)
     if ({-1'b1 == w1}) // when w1 = 2'b01 this should not be true
       r1 <= 1'b1;
endmodule // top

I have added a zip file which contains a Vivado tcl file and a test bench to recreate the error. Everything can be run using ./run.sh with the included testbench.

This happens on Vivado 2019.1 on my Arch linux machine, and also hapens on Vivado 2018.3 on CentOS 6.

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Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎02-16-2014

回复: [Vivado 2019.1] Unsigned bit extension in if statement

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Hi @ymherklotz 

 

Thanks for reporting this issue. Able to reproduce this issue at my end and filed CR to fix this issue.

In curly braces if -2'b1 is used instead of -1'b1 vivado is creating correct netlist.

Hope you have workaround to move forward with your design.

 

Thanks,

Manusha

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3 Replies
Xilinx Employee
Xilinx Employee
194 Views
Registered: ‎02-27-2019

回复: [Vivado 2019.1] Unsigned bit extension in if statement

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Hi @ymherklotz ,

In your code :

 always @(posedge clk)
     if ({-1'b1 == w1}) // when w1 = 2'b01 this should not be true
       r1 <= 1'b1;

Could you remove "{}" and have a try? Because the curly braces is used as concatenation.If the vivado didn't report it , it might a bug.

And after synthesis , you can run post-synthesis functional simulation . Does it right ? 

 

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Visitor ymherklotz
Visitor
187 Views
Registered: ‎06-06-2019

回复: [Vivado 2019.1] Unsigned bit extension in if statement

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Hi @yangc ,

Yes, without the { } for concatenation in the if-statement, Vivado synthesises the piece of code correctly. However, a concatenation of only one element should be valid and give the same result. This was reduced from a piece of code that had a concatenation of multiple elements.

All the best,

Yann

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Xilinx Employee
Xilinx Employee
169 Views
Registered: ‎02-16-2014

回复: [Vivado 2019.1] Unsigned bit extension in if statement

Jump to solution

Hi @ymherklotz 

 

Thanks for reporting this issue. Able to reproduce this issue at my end and filed CR to fix this issue.

In curly braces if -2'b1 is used instead of -1'b1 vivado is creating correct netlist.

Hope you have workaround to move forward with your design.

 

Thanks,

Manusha

0 Kudos