05-29-2020 09:13 PM
I recently ported a design from Vivado 2018.2 to Vivado 2019.2. This design includes the NVDLA accelerator by NVIDIA. The latter has several instances of a dummy module, which I assume exists to prevent some tool from throwing errors during synthesis or simulation.
If I just run implementation without attempting to debug with the ILA, Vivado optimizes the dummy module away and no DRC error occurs, however, when I add the `mark_debug` attribute to some signals, which are a couple of levels of hierarchy higher in the design, with respect to the NVDLA, Vivado does not optimize the dummy module during synthesis. As a result Vivado fails DRC checks before opt_design, because it detects the dummy as a black box.
[Project 1-560] Could not resolve non-primitive black box cell 'NV_BLKBOX_SINK' instantiated as 'tiles_gen.accelerator_tile.tile_acc_i/NV_NVDLA_gen.noc_NV_NVDLA_i/NV_NVDLA_rlt_i/NV_nvdla_0/u_partition_o/u_NV_NVDLA_cdp/u_rdma/u_cq/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_0'. 4480 instances of this cell are unresolved black boxes. [third-party/accelerators/dma64/NV_NVDLA/out/nv_small_fpga/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v:395]
In the same condition and adding the same `mark_debug` attribute to the same set of signals I was not getting this error with Vivado 2018.2. Is there a workaround to mark the module as a dummy and prevent the DRC error?
06-06-2020 08:33 AM - edited 06-06-2020 08:33 AM
Hi @paul.mnt ,
Is it possible to share code snippet. How is dummy module defined and where are mark_debugs applied on those ?
Just to give some background, mark_debug applied on any port of module will prevent module boundary and module itself. By any chance are you connecting all nets you want to debug to "dummy" module and then apply mark_debug on those.
If thats the case you can apply mark_debug on net that you want visibility in ILA, it will be not optimized away.
Please let know more of the problem in case its not resolved .
06-17-2020 07:30 PM
I'm using Vivado 2019.1, I'm also having the same problem; the code would work fine before applying mark_debug but won't afterwards. The combined code is attached. The netlist cell in question is:
[Project 1-486] Could not resolve non-primitive black box cell 'design_1_RocketChipNVDLA_0_1_NV_BLKBOX_SINK_HD1629' instantiated as 'design_1_i/RocketChipNVDLA_0/inst/inst/nvdla/u_nvdla/nvdla_top/u_partition_o/u_NV_NVDLA_pdp/u_wdma/u_dat/u_dat0_fifo7/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_31' ["c:/Users/jsteward/IdeaProjects/rocket-zcu102/vivado/tvm_shell/tvm_shell.srcs/sources_1/bd/nvdla/src/main/resources/nvdla_small.preprocessed.v":32116]
The attach file function does not work on the forum, Google drive link for the code:
06-18-2020 04:16 AM
Thank you for your reply.
The mark_debug attribute is not anywhere in the entire NVDLA block, which includes several dummy instances deep down in the hierarchy.
I am adding the debug attribute to my code, around NVDLA and not on NVDLA ports.
It’s hard to share a snippet, because it’s a large project, but you can look at the repo, and particularly at this file:
I tried adding mark debug to the ports of this entity.
The NVDLA wrapper is placed by a script at line 161.
Again, the instances of the dummy block are inside NVDLA and levels of hierarchy down.
Vivado 2018.2 would still optimize the dummy block away, even with debug attributes. Vivado 2019.2, instead does not remove the dummy and throws the DRC error.