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EllenG
Visitor
Visitor
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Registered: ‎09-16-2020

Vivado 2019.2, synthesis subtraction logic

Hello,

       The following code after synthesis, the msb of c seems to be hardwired to logic 0;

always @*
begin
case (a)
               3'h0 : b = 13'd64 - {7'd0, c[ 5:0]};
               3'h1 : b = 13'd128 - {6'd0, c[ 6:0]};
               3'h2 : b = 13'd256 - {5'd0, c[ 7:0]};
               3'h3 : b = 13'd512 - {4'd0, c[ 8:0]};
               3'h4 : b = 13'd1024 - {3'd0, c[ 9:0]};
               3'h5 : b = 13'd2048 - {2'd0, c[10:0]};
               default : b = 13'd4096 - {1'd0, c[11:0]};
endcase
end

 

for example, when a =1, c=x40, b should be  x40. I ran a simulation with the synthesized netlist, b is x80. I ran another case a=1, c=x60, b is x60 in gate sim. It seems like the synthesized logic treats b=13'd128-x20 = x60. (x60 with the msb hardwired to 1'b0 is x20). 

 

Can anyone help? Thanks in advance.

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2 Replies
EllenG
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Registered: ‎09-16-2020

BTW, it seems this only happens with vivado 2019.1 and 2019.2. I synthesized with 2018.2 and 2020.1, the gate sim from the corresponding netlist (2018.2 or 2020.1) shows no issues with the msb being hardwire to logic zero. 

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markcurry
Scholar
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Registered: ‎09-16-2009

Please show the declarations for a, b, and c.

Thanks,

Mark

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