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jprice
Scholar
Scholar
396 Views
Registered: ‎01-28-2014

Vivado 2020.2 Projectless Build an Applying Constraints

A normal part of my build flow over the years has been to check timing post synthesis. I've recently setup a new build for a new board using Vivado 2020.2 and ran into something I've never seen before. I've got a projectless flow build that has a block design and a couple of Xilinx IP with very important timing constraints. My build sources a BD tcl file and builds that as well as calls read_ip/generate_targets/synth_ip for the IP. What I noticed is post synthesis is that the IP constraints were not applied, only what I manually read in with read_xdc. So most of my design post synthesis showed no clocks. However after route design everything was applied! This is really weird to me as I've seen Vivado make synthesis optimizations based on clock rates. It also makes doing post synthesis timing analysis harder. I was able to open a checkpoint and in the gui go tools -> timing -> edit timing constraints. From there I could hit apply and this would work. However I see no way to automate this as that produces no tcl commands in the journal. Can someone provide some insight into what is happening here and what I can do about it?

Thanks!

3 Replies
anusheel
Moderator
Moderator
299 Views
Registered: ‎07-21-2014

Hi @jprice ,

Can you please share a snippet of the script for us to understand the flow better?

Thanks
Anusheel 

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jprice
Scholar
Scholar
227 Views
Registered: ‎01-28-2014

@anusheel,

Rough approximation given below. This is just synthesis. There are many VHDL files, but just one BD TCL file and one Vivado IP file so far. Do you need other information?

 

set_part xcku5p-ffvb676-2-e

# Read in block diagram
source bd_tcl_file.tcl
set bd_source_file /path_to_bd_file.bd
read_bd $bd_source_file

# Ensures the block design is not set for OOC flow
set_property SYNTH_CHECKPOINT_MODE None [get_files $bd_source_file]

# Generate files from build design
generate_target all [get_files $bd_source_file]      

#Create a top level wrapper
make_wrapper -files [get_files $bd_source_file] -top

set bd_wrapper_source_file /home/domain/jprice/Bit_Bucket/Xylem/Xylem-Dev/kcu116_testbed/build/../builds/temp/kcu116_testbed_bd/hdl/kcu116_testbed_bd_wrapper.vhd
read_vhdl -vhdl2008 $bd_wrapper_source_file
   
# MANAGED IP
read_ip ip.xci
generate_target {instantiation_template synthesis} [get_ips ip_name]
synth_ip [get_ips ip_name]

#Read in VHDL files
read_vhdl -vhdl2008 -library lib_name source_file.vhd

read_xdc /home/domain/jprice/Bit_Bucket/Xylem/Xylem-Dev/kcu116_testbed/build/../constraints/kcu116.xdc
set_property top top_level [current_fileset]
synth_design -flatten_hierarchy rebuilt -top top_level -part xcku5p-ffvb676-2-e -bufg 0 -assert

write_checkpoint -force post_synth.dcp

 

anusheel
Moderator
Moderator
158 Views
Registered: ‎07-21-2014

Hi @jprice ,

Just a quick check, are you able to see the clocks and constraints before writing the .dcp file by using get_* (get_clocks) on the synthesized design?
Please make sure there are no black boxes at this stage as it will ensure the sub-module IP runs are also loaded. 

Also, do you see any issues/warnings in write_checkpoint phase? 

Thanks
Anusheel 

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