Vivado GDpGen::implementDivMod(DFNode*, bool): Assertion `TBD' failed.

[cliffordwolf]

When I try to synthesize the following module with Vivado 2013.4

module issue_014(a, b, y);
  input [1:0] a;
  input [2:0] b;
  output [3:0] y;
  assign y = $signed(a / b);
endmodule

I get the following error message:

vivado: /proj/buildscratch/builds/2013.4/continuous/20131209165331/src/ext/oasys/src/syn/gen/gencore/dp/GDpGenDivMod.cc:324: void GDpGen::implementDivMod(DFNode*, bool): Assertion `TBD' failed.
Abnormal program termination (6)

I'm not sure if this qualifies as a bug report or simply as a reminder that there is a "TBD" assert in Vivado production code. Either way: This is in there for a while now which leads me to the assumption that it was forgotten that there is something left to be done in GDpGen::implementDivMod()..

This is the TCL script I was using to build the module:

read_verilog issue_014.v
synth_design -part xc7k70t -top issue_014
write_verilog -force issue_014_netlist.v

Note: This is a bug report. I don't need support.

[hj]

Is there any reason for output being 4 bit long?


As your inputs are 2 bits & 3 bits long. If you make your output bits equivalent to input bits then there is no error.

Thanks

[cliffordwolf]

har**bleep** wrote:

Is there any reason for output being 4 bit long?

Only to demonstrate the bug. As I have written: This is a bug report, not a support request. I'm not trying to get help from Xilinx to get my design running, I want to help Xilinx to find and fix the bugs in their software and thus improve the quality of their product.

The 4 bit long output is correct synthesizeable Verilog code, so Vivado should except it as input and not assert. It is not a tragedy that it does not process this input atm. I'm not complaining. I'm trying to raise attention to the problem because it would be sad to have this behavior in there for the years to come, just because the information about the issue does not get from me to the people who are in the possition to fix it for the next release.

PS: Especially when using a lot of auto-generated Verilog code (e.g. from a HLS tool), a bug like this can be a showstopper.

[achutha · Accepted solution]

Hi ,

Thanks for pointing to the bug.
I was able to reproduce the issue and it seems a bug.
I will take up the next steps in reporting this as a bug and will provide you with the CR reference.

Regards,
Achutha

[achutha]

Hi Clifford,

Thanks for waiting on this.

This issue is fixed in latest build of 2014.2  release.

Regards,
Achutha