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Explorer
Explorer
13,413 Views
Registered: ‎05-07-2012

Vivado IP Catalog Cores are Black Boxes during synthesis

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Hello,

 

I'm noticing that during synthesis with Vivado that the cores that I generated with the Vivado IP Catalog are all treated as black boxes and I'm not getting any kind of read on the amount of Block Ram that I'm using after the Synthesis is over. 

 

I'm wondering if and why Vivado has to treat its own cores as black boxes? 

 

Is there some way to get  the Vivado Synthesizer to include the cores in the Synthesis process so I can get a better read on resourse utilization? 

 

Thank you.

 

 

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Explorer
Explorer
22,757 Views
Registered: ‎05-07-2012

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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The web case engineer got back to me with the precise answer to my problem so I'll mark this as "solved".  Thanks.

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Xilinx Employee
Xilinx Employee
13,400 Views
Registered: ‎09-20-2012

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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Hi,

In Vivado We have out of context synthesis enabled for ip's by default. Hence top level synthesis treats ip's as black boxes. The netlists for ip's are read in during implmenetation.

To get the correct utilization after synthesis open the synthesized design and run report_utilization command from tcl console to get the correct utilization numbers.

Opening the synthesized design loads in the ip checkpoints as well in to the memory and hence the utilization reported will be correct.

Thanks,
Deepika.
Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
13,391 Views
Registered: ‎02-06-2013

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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Hi

 

You can disable the OOC as shown in the below snapshot for the IP's used in your design so that Vivado Synthesizer will include these cores in the Synthesis process  not treat them as Black boxes.

 

IP_OOC_disable.png

Regards,

Satish

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Moderator
Moderator
13,386 Views
Registered: ‎07-21-2014

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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Hi,

 

Refer below link (page no. 14) for more information on global synthesis:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug896-vivado-ip.pdf

 

Thanks,
Anusheel
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Thanks
Anusheel
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Explorer
Explorer
13,348 Views
Registered: ‎05-07-2012

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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Satish,

 

Your answer looks like the closest to the solution but I'm not understanding what exactly to do.  I'm aware of both the "Generate Output Products" and the "Out of Context Settings" Dialogs but I'm not clear about exactly what to do with them to disable the OOC.  I think making the OOC default was a dumb design decision and would like to have the default be the "Generalized Synthesis" I read about these in the "Designing with IP" Users Manual.  The manual blabbered on and on about what these two synthesis modes mean but I didn't see any nuts and bolts procedure on how to select or disable either (classic Xilinx). 

 

So, exactly how do I disable the OOC through these two dialogs?

 

Thanks.

 

Roger

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Explorer
Explorer
13,345 Views
Registered: ‎05-07-2012

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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Hello Anusheel,

 

I read parts of that user guide.  It rambled on about what OOC and Generalized Synthesis are but nowhere near as I can tell did it say exactly how to select one or the other.

 

Thanks.

 

Roger

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Explorer
Explorer
22,758 Views
Registered: ‎05-07-2012

Re: Vivado IP Catalog Cores are Black Boxes during synthesis

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The web case engineer got back to me with the precise answer to my problem so I'll mark this as "solved".  Thanks.

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