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Newbie
Newbie
415 Views
Registered: ‎08-28-2019

Vivado Pre-defined Macros

Hi,

 

Does Vivado define any macros that would allow the designer to select code which depends on the version of Vivado, or ISE, or even whether the synthesizer is Vivado or ISE?

I've seen the question asked, but no one has answered.  This is a common and very useful feature of simulators and synthesizers, especially when blocks such as DCMs are changed between FPGA generations, or if language features are added between synthesizer generations.

Thanks,

Richard

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3 Replies
384 Views
Registered: ‎01-22-2015

@gvrichard 

VHDL has the "if-generate" statement that allows you to activates specific parts of your HDL source code based on a "test result".  The "test result" could be the value of a std_logic constant that you set in the VHDL package file for your project.

For example,

constant using_Vivado : std_logic := '1'; --1=Vivado, 0=ISE
.
.

GEN1: if (using_Vivado = '1') generate
    --place VHDL here that you only want to use in Vivado
end generate GEN1;

GEN2: if (using_Vivado = '0') generate
    --place VHDL here that you only want to use in ISE
end generate GEN2;

 

See page 194 of UG901(v2020.1) for more on "if-generate".

Cheers,
Mark

Xilinx Employee
Xilinx Employee
341 Views
Registered: ‎05-14-2008

Agree with markg@prosensing.com 

And Verilog has "Generate Statements" for the same. See UG901 v2020.1, Page 264.

Vivado does not have existing Macros for this kind of settings. User has to get latest and updated information for different versions/devices/tools.

-vivian

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Newbie
Newbie
296 Views
Registered: ‎08-28-2019

Hi,

Thanks for the responses, but neither answer my question at all.  Of course I know how to use ifdefs, etc.  Been using them for more years than I'll admit to. 

I'll ask again, does Vivado define any macros that would allow the designer to select code which depends on the version of Vivado, or ISE, or even whether the synthesizer is Vivado or ISE? 

I'm talking about predefined macros embedded and defined in the synthesizer or simulator, not a macro that I define myself.

An example might be __VIVADO__, or __ISE__ and/or __XILINX__, and/or __VIVADO_19.2__, or ??? 

Other simulators, and every language compiler in existence contain pre-defined macros to allow the designer to write portable code among different compilers, or to manage differences between compiler/simulator/synthesizer versions.

Publishing a list of predefined macros for Xilinx products would be very useful to have in the documentation of the relevant product.

Thanks,

Richard

 

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