01-02-2019 07:35 AM
I have a Zync project in Vivado 2016.2. I could easily modify and compile it. However, after changing some constraints and commenting them it can't finish the synthesis and waits in the state forever. I took a look at some posts like Vivado can't finish Synthesis and changed FSM_encoding from default to one_hot. But, it is still in the synthesis and seems that can't get out it. Below is the last message in the log:
I appreciate any help.
Thanks in advance.
01-02-2019 07:41 AM
01-02-2019 10:17 AM
It's been a long time since I started it say 1 day. Besides, as I explained before this code was running and synthesizable before. None of the mentioned cases applies to this project.
01-02-2019 10:25 AM
If you back out the recent change, I wonder if it would work again. (If so, that may help focus the search).
If you are willing to post the Vivado Project, I am willing to try it on my version (2018.3)... No promises for success.
If you want to keep it private... a moderator may be able to help with a private post.
Hope that helps
01-02-2019 11:49 PM
I have a problem with Vivado 2016.2 which stays in synthesis forever. It would be so clear if you read the first post. I need your help to solve this issue. What should I do? Please advise. I am short of time and can't be waiting for some guesses from forum visitors.
Thanks in advance,
01-03-2019 09:22 PM
Could you please let us know the changes in details? If the changes are only done in constraints, what happens when you disable/remove XDC file from the project? This will help us to understand whether this is hang is coming from RTL or XDC.
Is there any possibility of migrating to latest 2018.3 version?
Also, can you try to launch vivado as "vivado -stack 2000" and let us know the results.
01-07-2019 06:18 AM
Thank you for the answer. I was working on something else. I have to say that total changes are just timing constraint and some simple logic. I don't expect these simple changes affect synthesis. If you see the first post it is obvious that it got stuck in synthesis, not PAR. So, doesn't make sense any changes in timing constraints impact synthesis. Anyway, regarding the software update, if you are sure that this would resolve our problem and it doesn't cost anything seriously please inform me. then I will ask my colleagues to contact your representative.
01-07-2019 09:55 PM
Synthesis specific constraints(timing constraints) impacts the synthesis run. Please make sure wildcards * are used correctly with get_pins/get_nets/get_cells and design is properly constrained.
Regarding the 2018.3 upgrade, if this issue was already reported or found in 2018.2/previous versions then we expect the 2018.3 to complete the design run successfully.
If you can share the project with us, we will be able to provide a fix or workaround.