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Visitor
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Registered: ‎08-31-2020

Vivado RTL implementation

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Hi Xilinx Team,

I have a ASIC design and ported to the FPGA, and wanted to check resource utilization.
FPGA Choosenxczu9eg-ffvb1156-3-e
Vivado Version used : 2018.3 ( cannot move to latest version due to Licensing issues from company side) 
# SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
Also tried with 2020.1 version ( I am using the trail period)

Question :1  (High Priority)
Resource Utilization : My design top level ports are mentioned below which need to connect to the external interface.
I have given PIN LOCATIONS in the XDC , and  create_clock constraint in the XDC as shown below 
-----------------------------------------------------------------------------------------------------------------
create_clock -period 12.698 -name extclk -waveform {0.000 5.000} [get_ports clk]
set_property PACKAGE_PIN AN11 [get_ports rst]
set_property PACKAGE_PIN AF10 [get_ports mosi]
set_property PACKAGE_PIN AG1[get_ports miso]
set_property PACKAGE_PIN AH7 [get_ports data0n]
set_property PACKAGE_PIN AH8 [get_ports data0p]
set_property PACKAGE_PIN AE12 [get_ports clk0n]
set_property PACKAGE_PIN AG11 [get_ports clk0p]
set_property PACKAGE_PIN AN11 [get_ports {spare0 [3]}]
set_property PACKAGE_PIN AJ7 [get_ports {spare0 [2]}]
set_property PACKAGE_PIN AM3 [get_ports {spare0 [1]}]
set_property PACKAGE_PIN AP1 [get_ports {spare0 [0]}]
set_property PACKAGE_PIN AK12 [get_ports {test_monitor[3]}]
set_property PACKAGE_PIN AJ12 [get_ports {test_monitor[2]}]
set_property PACKAGE_PIN AM11 [get_ports {test_monitor[1]}]
set_property PACKAGE_PIN AL11 [get_ports {test_monitor[0]}]
---------------------------------------------------------------------------------------------
--------------------------------------------------------------- PICTURE 1 
entity top_level is  
    port (
      clk : in std_logic;
      rst : in std_logic;
      mosi : inout std_logic;
      miso : out std_logic;
      data0n : out std_logic;
      data0p : out std_logic;
      clk0p : out std_logic;
      clk0n: out std_logic;
      spare0 : in std_logic_vector(3 downto 0);
      test_monitor: inout std_logic_vector(11 downto 0)
);
end top_level ;
architecture rtl of top_level is 
begin
 ( I do have multiple  instantiations)
  u_m0 : module_0
  port map (

  );

 u_m1: module_1 
   port map (
  );

u_m2 : module_2 
  port map (

);
end rtl;

My scinerio:  Note ** module_2 contains 10 inputs and 10 outputs and Output has a driver, input port exists but has no logic inside the module. 
-----------------------------------------------------------------
When i run the Synthesis and wanted to check how much the design resource utilization ? Synthesis run is successful and I get the Utilization as attached in CLB.JPG.Most of my design got pruned or trimmed. Why ?
Top level ports are connected to the PIN constraints and also to the design. 

 
 

Question 2: (High Priority)
RPBF #1 Device port spare0[0] expects both input and output buffering but the buffers are incomplete.
I have seen some previous POSTs related to this and i was not clear.
So when i open the Elaborated design and performed the Report DRC i get the above message.
Can you please tell me how do i connected my inout  ports to the PIN LOC constraints ? My top level pins looks like shown in PICTURE 1 above.

Question 3: (Medium priority)
Synth 8-6777 : Could not find entity adder used in configuration spec. Use the full path with library.
I
have VHDL configuration concept in my Design, 
VHDL file name : chip_top.vhd
Verilog File name: adder.v
-----------------------------------------------------------
configuration chip_cfg  of chip_top is 
   for rtl 
      for u_adder : adder
         use entity work.adder(rtl);
      end for;
end configuration chip_cfg  ;
------------------------------------------------------------------
When i synthesis my top_level design  i get the following error as shown above colored RED
For the question 3 currently i wrote a VHDL wrapper for the adder.v to adder_wrapper.vhd and it moved on ....
Could you please tell me some efficient way to handle this issue. 


Kindly help me out in resolving this issue at earliest.

Thanks Regards
Pranesh
email id : Pranesh.Madeti@onsemi.com

Pranesh
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CLB.JPG
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1 Solution

Accepted Solutions
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Moderator
Moderator
152 Views
Registered: ‎07-21-2014

@Pranesh,

It would be good if you can open a separate thread for each question. 

Question :1  (High Priority)
Resource Utilization : My design top level ports are mentioned below which need to connect to the external interface.

>>> The tool may remove the logic if the value coming to the ports are always 1/0. Please make sure the connection to output ports are valid, can you please show us the RTL or code snippet? 

For inout connection usage, please refer the UG901.

 
 

Question 2: (High Priority)
RPBF #1 Device port spare0[0] expects both input and output buffering but the buffers are incomplete.
I have seen some previous POSTs related to this and i was not clear.
So when i open the Elaborated design and performed the Report DRC i get the above message.

Can you please tell me how do i connected my inout  ports to the PIN LOC constraints ? My top level pins looks like shown in PICTURE 1 above.

>>> If the inout is used at the top, tool will try to convert them to tristate buffers. Please refer the UG901 OBUF expample codes. 

Question 3: (Medium priority)
Synth 8-6777 : Could not find entity adder used in configuration spec. Use the full path with library.

>>> The usage looks unsupported under mixed-language support section of UG901. 

UG901: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

Thanks
Anusheel 

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5 Replies
Highlighted
Moderator
Moderator
261 Views
Registered: ‎04-24-2013

Hi @Pranesh ,

From the look of the utilization report I am guessing that your synthesized design just has 5 LUTS driving the output ports?

The reason this is happening is that if you have Inputs connected to no logic and the outputs connected to drivers then the design can never change states. So the tools see this and optimize everything away just leaving drivers for the outputs. This is expected.

Best Regards
Aidan

 

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Highlighted
Xilinx Employee
Xilinx Employee
202 Views
Registered: ‎06-27-2018

Hi @Pranesh,

If possible, please provide a testcase for the optimization issue. Please send me your email ID in private message on forum , I will send you ezmove link.

Also, for multiple queries, please consider creating multiple threads (1 query in each thread), in this way the posts will get more visibility. 

~Chinmay

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Highlighted
Moderator
Moderator
153 Views
Registered: ‎07-21-2014

@Pranesh,

It would be good if you can open a separate thread for each question. 

Question :1  (High Priority)
Resource Utilization : My design top level ports are mentioned below which need to connect to the external interface.

>>> The tool may remove the logic if the value coming to the ports are always 1/0. Please make sure the connection to output ports are valid, can you please show us the RTL or code snippet? 

For inout connection usage, please refer the UG901.

 
 

Question 2: (High Priority)
RPBF #1 Device port spare0[0] expects both input and output buffering but the buffers are incomplete.
I have seen some previous POSTs related to this and i was not clear.
So when i open the Elaborated design and performed the Report DRC i get the above message.

Can you please tell me how do i connected my inout  ports to the PIN LOC constraints ? My top level pins looks like shown in PICTURE 1 above.

>>> If the inout is used at the top, tool will try to convert them to tristate buffers. Please refer the UG901 OBUF expample codes. 

Question 3: (Medium priority)
Synth 8-6777 : Could not find entity adder used in configuration spec. Use the full path with library.

>>> The usage looks unsupported under mixed-language support section of UG901. 

UG901: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

Thanks
Anusheel 

View solution in original post

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Visitor
Visitor
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Registered: ‎08-31-2020
Hi Anusheel ,
My issues got resolved , thanks a lot for your inputs..
Pranesh
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Highlighted
Moderator
Moderator
34 Views
Registered: ‎07-21-2014

@Pranesh That's great. Can you please mark the appropriate answer as an accepted solution that helped to resolve the issue?

Thanks
Anusheel 

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