04-08-2015 01:41 AM
I have been trying to synthesize the design containing ARM IP using Vivado 2014.2 on Xilinx FPGA VC707 boards
I have run into a Vivado synthesis issue in including the appropriate files in the RTL design hierarchy of ARM IP as explained by the simple example attached here
As far as I know , Vivado Synthesis settings allows to have only 1 search path for "include_dir" whereas we need 2 search paths for the current design .
synthesis setting : -include_dirs ../../creative.srcs/sources/imports/creative/a/
ERROR: Synth 8-1766 cannot open include file a_def.v /home/shefali/creative/creative.srcs/sources/imports/creative/b/f_b1.v:4
Design hierarchy is as below
f_a1.v has "include "b_def.v"
f_b1.v has "include "a_def.v"
Kindly suggest a workaround to this problem WITHOUT changing the RTL as it's an ARM IP.
04-08-2015 01:43 AM
You can use curly braces to pass multiple directory paths to the -include_dirs option of synth_design.
For more details refer to this thread http://forums.xilinx.com/t5/Vivado-TCL-Community/synth-design-include-dirs-and-multiple-include-directories/td-p/311871
04-08-2015 02:28 AM
Thanks for the reply
When I use curly braces to specify multiple include directories and run synthesis, I run into below errors
ERROR: [Synth 8-988] a is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:1]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:1]
ERROR: [Synth 8-988] b is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:3]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:3]
ERROR: [Synth 8-988] c is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:5]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:5]
ERROR: [Synth 8-988] d is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:7]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:7]
ERROR: [Synth 8-988] e is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:9]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:9]
ERROR: [Synth 8-988] f is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:11]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:11]
ERROR: [Synth 8-988] z is already declared [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:12]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/shefali/xilinx_project/creative/creative.srcs/sources_1/imports/creative/b/b_def.v:12]
ARM IP has multiple directories with RTL files having "includes" that reside in different sub directories and the parameters definition also duplicates between the various includes.
However, Modelsim compiles the entire directory structure fine with multiple include dir without giving this " already declared" error
Please let me know the workaround in Vivado
04-09-2015 11:38 PM
Can anybody let me know the way in Vivado to synthesize with "include" option including several files residing in different directories having same parameter declarations.
Please suggest a workaround to the error I encounter in the simple illustration in the earlier mail.
Does Vivado support the above case ?
06-23-2015 02:49 PM
Redeclaring a paramater or module is illegal in Verilog and that is what this error is telling you. I do no know how you set up Modelsim or what they are doing differently - but you will have to sort out and remove the duplicates to get this to compile correctly.
Also be aware that there be synthesis translate on/off pragmas and the fact that a simulation tool parsed your files does not mean that they are syntactically correct for the synthesis tool.
07-10-2017 01:01 AM
I am using vivado 2017.2. When I try to synthesize, I am getting the similar error.
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/x02/home/ku060_pcie_core/main_source/pci_config_defs.v:4]
ERROR: [Synth 8-988] CONF_MOD_PCI_COMMON_BASE is already declared [/x02/home/ku060_pcie_core/main_source/pci_config_defs.v:4]
[Extract from pci_config_defs.v. This file contain only param defines.]
[line 4] localparam CONF_MOD_PCI_COMMON_BASE = 0;
I have verified that there are not duplicates of the same parameter anywhere in the project. I am getting this for all the parameter in the file. I have also modified that file to be a global include file and set the file type to be a verilog header. But still getting the issue.
Please help on this.